No Subject

[Ashok Rajamani <arajamani@rocketmail.com>]

Hi All,
  Congratulations on the first year anniversary of
OpenCores. I write this mail in response to a call for

new projects. 
  Here is what I have in mind. 
- My RTL coding preference is Verilog.
- I'd like to do some RTL design work writing mainly 
  synthesizable code.
- I plan to use functional formal verification
  tools to do design verification as the code
  develops.     

For the benefit, of those who have not heard about 
formal verification, here is my two cents on it. 
Although synonymous with equivalency checking (or
comparing two netlists for equivalence, be they
RTL-to-gate or gate-to-gate), formal verification can
be classified into two categories. 

1. Implementation verification(ie.equivalency
checking) to check if your synthesizer synthesized a
gate-level netlist that retains the functionality of
your RTL. This has found commercial success. 

2. Design verification(ie.model checking) to check if
you really implemented what you intended to implement.
This is a harder problem, the solution for which has
to-date been dismissed by the majority of the design
community as having limitations and complexity
problems. 

The traditional simulation having become a
verification bottleneck, designers are forced into
looking at orthogonal alternatives. 

Let me stop the marketing pitch here by asking anyone
interested in more information to mail me. 
If you have any ideas for new design projects do count
me in to help.  
Thanks for your attention,
Ashok. 



  
 

 



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