----- Original Message -----
Sent: Friday, April 06, 2001 5:30
AM
Subject: [oc] i am developing a powerful
processor compatible with arm
it contain instruction cache ,data cache,instruction
prefetch buffer ,and a simple tomasulo structure and reorder buffer just like
a simple DLX proceesor.
now,the cache controller and prefetched buffer can be
synthesize ,
the behavior description of memory controller have been
ok,
the fetch and decode pipeline stage is also ready to be
synthesize,
the tomasulo structure and reorder buffer is under
developing
i think it can take its place as a high end embedded
processor or a midel performance general processor.
i want some help to produce a whole useful
system
by the way,my English is poor,the spell of some words in
this mail is error,i am very sorry for
that