[oc] How about a C-FLEA core?

[Dave Dunfield <dave@dunfield.com>]

Hello, this is my first contact with the "cores" group...

My name is Dave Dunfield, my company Dunfield Development Systems is
reasonably well known as a vendor of development tools for small 8/16
bit microcontrollers... See http://www.dunfield.com for more info.

I have a CPU architecture/instruction set which I created a few years
ago, called the C-FLEA, which is designed to be simple and optimized
as a target for a 'C' compiler. This architecture is very space efficent,
compiled code usually comes out more than 30% less for this processor
than when compiled for other "native" microcontrollers (this is using
my own Micro-C compiler, which has the same front end for all CPU's).

To date, the C-FLEA has only been available as a "Virtual Machine",
implemented in software on another platform... It has worked well in
this role, and proven fairly popular.

I have always had the idea in the back of my mind about having the
C-FLEA architecture put "in silicon"... When I heard about opencores,
I decided to post this message, and see if there would be anyone
interested in such a project.


C-FLEA Technical information:
-----------------------------
This is a proven architecture. I have virtual machine implementaions
available for quite a few target processors, as well as a fairly
comprehensive PC based simulator, Assembler, C compiler and other
tools.

There are four registers: Accumulator (16 bits), Index register (16
bits), Program counter (16 bits), and SP (8 or 16 bits depending on
implementation).

There are a total of 61 instruction, which are organized as follows:
  25 Memory referencing instructions **
   8 Compare modifier (flags) instructions
  10 Transfer instructions (JMP, CALL, RET etc.)
   6 Stack manipulation instructions
  12 Misc. instructions

** Ths 25 Memory referencing instructions have 8 "addressing modes"
   each, for a total of 200 opcodes.

All opcodes are 1 byte in size. The opcode map is filled from
00-EB. EC-FF remain unused at this time, with the virtual machine
implementation, I leave these open as "User Defined" instructions.

The instruction set has been organized to be very easy to decode.
The 8-bit opcode contains specific bit fields to identify the
type of opcode and addressing modes (where applicable). A complete
C-FLEA Virtual Machine implementation in software usually takes
only about 1K of native machine code. If desirable, I would have
no problem re-arranging the opcode map to optimize the hardware
decoding... In this regard, it is really quite flexible.

The C-FLEA is intended to be a very small CPU, it's architecture
allows for up to 64k of memory. Due to the efficency of the instruction
set, this represents a fairly large amount of functional logic to the
application programmer...



I would like to explore the possibility of creating an open-core for
the C-FLEA architecture. I do not have experience with CPU Core design,
however I do have a lot of experience from a user/programming/interfacing
point of view, and I can provide detailed documentation and help with
the C-FLEA architecture.

I have a complete specification for the C-FLEA architecture which I can
send to anyone who is interested in helping me look into this further.

Please contact me if you are interested in such a project.

Regards,
Dave Dunfield

(PS: The MC321EMB.ZIP demo toolset from the download area of my web
page is based on the C-FLEA technology... This has a demo compiler,
assembler and simulator, and minimal information on the C-FLEA VM..
if anyone would like to take a quick look).

-----------------------------------------------------------------------
dave@     Dave Dunfield - Dunfield Development Systems
dunfield. Box 31044  Nepean Ontario Canada K2B 8S8     FAX:613-256-5821
com       Low $ embedded SW development tools   http://www.dunfield.com