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Re: [pci] RST_I net missing?
Hi Miha,
>If you are using GUEST implementation of the bridge, RST_I is not connected
>anywhere.
>I guess the synthesis optimizes it away, and then the constraint is no
>longer valid.
thanks for the hint, you put me on the right track. In fact GUEST bridge was
right and if instead of RST_I, I use RST_O the bit file will be created
successfully.
I going to try the example of the WISHBONE tutorial (A.6.1 in the spec) "Simple
8-bit WISHBONE SLAVE output port"(page 79) using POINT TO POINT interconnection
(page 73) there is shown that RST_I of WBmaster should be connected to RST_I of
WBslave.
Could you please have a look to the attached schematic which shows how I connect
the PCI-bridge (Core 1, verilog) to the WB-Slave application (Core 2, VHDL).
Is this connection setup right?
and
Can I give 8kHz pulses to INT_I and will this generate 8kHz pulses at INTA# to
generate interupts in GUEST mode? (Simple Sound Card application is my first
goal ;-)
Thanks in advance,
Regards/Nico.
PS: for the redefine warnings; doesn't something like C's
#IFNDEF pci_constants.v
exits in verilog?
>About the warnings - I can see the compiler is complaining about
>redefinition of the defines.
>It looks like the defines are treated as global, which should not be the
>case.
>I can see that the first file is compiled without warnings, all the others,
>which include the pci_constants.v, produce a lot of warnings.
>
>I would say this is nothing to worry about.
>
>Regards,
>Miha Dolenc
>
>----- Original Message -----
>From: "Nico Weling" <eedniwe@eed.ericsson.se>
>To: <pci@opencores.org>
>Sent: Friday, June 20, 2003 9:47 AM
>Subject: [pci] RST_I net missing?
>
>
>> Hi,
>>
>> I'm using the TOP.v file of the pci_bridge only (no CRT application)
>>
>> If I create an constrains file in which I connect only all PCI related
>pins I
>> can successfully generate a working bit file.
>>
>> But if I, in addition to the previous ucf-file, connect RST_I net to an
>physical
>> pin I get the following error message:
>>
>>
>============================================================================
>====
>> ERROR:NgdBuild:755 - Line 10 in 'aimsblaster4wbm_io8.ucf': Could not find
>net(s)
>>
>> 'RST_I' in the design. To suppress this error use the -aul switch,
>specify
>> the correct net name or remove the constraint.
>>
>============================================================================
>====
>>
>> TOP.v:
>> --------------------------------
>> ...
>> module TOP
>> (
>> ...
>> RST_I,
>> ...
>>
>> // WISHBONE system signals
>> ...
>> input RST_I ;
>> ...
>> --------------------------------
>>
>> Attached is my .ucf file. Does someone see what I did wrong?
>>
>> Regards/Nico.
>>
>>
>> PS: I changed the ucf file using "Xininx PACE" and there RST_I was in the
>list
>> of IO's.
>>
>>
>> __________________________________
>> Nico Weling
>> System Designer
>> Ericsson Eurolab Deutschland GmbH
>> Verification Tool Design
>>
>> Tel: +49 2407 575 5217
>> Fax: +49 2407 575 651
>> Dect:+49 2407 575 89339
>> mailto:Nico.Weling@eed.ericsson.se
>> __________________________________
>>
>>
>
>
>----------------------------------------------------------------------------
>----
>
>
>> #PACE: Start of Constraints extracted by PACE from the Design
>> NET "WE_O" LOC = "P84" ;
>> NET "TRDY" LOC = "P18" ;
>> NET "TRDY" IOSTANDARD = PCI33_5;
>> NET "STOP" LOC = "P21" ;
>> NET "STOP" IOSTANDARD = PCI33_5;
>> NET "STB_O" LOC = "P95" ;
>> NET "SERR" LOC = "P23" ;
>> NET "SERR" IOSTANDARD = PCI33_5;
>> NET "RST_I" LOC = "P149" ;
>> NET "RST_I" IOSTANDARD = LVTTL;
>> NET "RST" LOC = "P192" ;
>> NET "RST" IOSTANDARD = PCI33_5;
>> NET "REQ" LOC = "P194" ;
>> NET "REQ" IOSTANDARD = PCI33_5;
>> NET "PERR" LOC = "P22" ;
>> NET "PERR" IOSTANDARD = PCI33_5;
>> NET "PAR" LOC = "P24" ;
>> NET "PAR" IOSTANDARD = PCI33_5;
>> NET "MDAT_O<7>" LOC = "P98" ;
>> NET "MDAT_O<6>" LOC = "P100" ;
>> NET "MDAT_O<5>" LOC = "P94" ;
>> NET "MDAT_O<4>" LOC = "P96" ;
>> NET "MDAT_O<3>" LOC = "P97" ;
>> NET "MDAT_O<2>" LOC = "P99" ;
>> NET "MDAT_O<1>" LOC = "P101" ;
>> NET "MDAT_O<0>" LOC = "P102" ;
>> NET "IRDY" LOC = "P17" ;
>> NET "IRDY" IOSTANDARD = PCI33_5;
>> NET "INT_I" LOC = "P58" ;
>> NET "INTA" LOC = "P191" ;
>> NET "INTA" IOSTANDARD = PCI33_5;
>> NET "IDSEL" LOC = "P3" ;
>> NET "IDSEL" IOSTANDARD = PCI33_5;
>> NET "GNT" LOC = "P193" ;
>> NET "GNT" IOSTANDARD = PCI33_5;
>> NET "FRAME" LOC = "P16" ;
>> NET "FRAME" IOSTANDARD = PCI33_5;
>> NET "DEVSEL" LOC = "P20" ;
>> NET "DEVSEL" IOSTANDARD = PCI33_5;
>> NET "CLK_I" LOC = "P77" ;
>> NET "CLK" LOC = "P185" ;
>> NET "CLK" IOSTANDARD = PCI33_5;
>> NET "CBE<3>" LOC = "P199" ;
>> NET "CBE<3>" IOSTANDARD = PCI33_5;
>> NET "CBE<2>" LOC = "P15" ;
>> NET "CBE<2>" IOSTANDARD = PCI33_5;
>> NET "CBE<1>" LOC = "P27" ;
>> NET "CBE<1>" IOSTANDARD = PCI33_5;
>> NET "CBE<0>" LOC = "P37" ;
>> NET "CBE<0>" IOSTANDARD = PCI33_5;
>> NET "AD<31>" LOC = "P195" ;
>> NET "AD<31>" IOSTANDARD = PCI33_5;
>> NET "AD<30>" LOC = "P200" ;
>> NET "AD<30>" IOSTANDARD = PCI33_5;
>> NET "AD<29>" LOC = "P201" ;
>> NET "AD<29>" IOSTANDARD = PCI33_5;
>> NET "AD<28>" LOC = "P202" ;
>> NET "AD<28>" IOSTANDARD = PCI33_5;
>> NET "AD<27>" LOC = "P203" ;
>> NET "AD<27>" IOSTANDARD = PCI33_5;
>> NET "AD<26>" LOC = "P204" ;
>> NET "AD<26>" IOSTANDARD = PCI33_5;
>> NET "AD<25>" LOC = "P205" ;
>> NET "AD<25>" IOSTANDARD = PCI33_5;
>> NET "AD<24>" LOC = "P206" ;
>> NET "AD<24>" IOSTANDARD = PCI33_5;
>> NET "AD<23>" LOC = "P4" ;
>> NET "AD<23>" IOSTANDARD = PCI33_5;
>> NET "AD<22>" LOC = "P5" ;
>> NET "AD<22>" IOSTANDARD = PCI33_5;
>> NET "AD<21>" LOC = "P6" ;
>> NET "AD<21>" IOSTANDARD = PCI33_5;
>> NET "AD<20>" LOC = "P7" ;
>> NET "AD<20>" IOSTANDARD = PCI33_5;
>> NET "AD<19>" LOC = "P8" ;
>> NET "AD<19>" IOSTANDARD = PCI33_5;
>> NET "AD<18>" LOC = "P9" ;
>> NET "AD<18>" IOSTANDARD = PCI33_5;
>> NET "AD<17>" LOC = "P10" ;
>> NET "AD<17>" IOSTANDARD = PCI33_5;
>> NET "AD<16>" LOC = "P14" ;
>> NET "AD<16>" IOSTANDARD = PCI33_5;
>> NET "AD<15>" LOC = "P29" ;
>> NET "AD<15>" IOSTANDARD = PCI33_5;
>> NET "AD<14>" LOC = "P30" ;
>> NET "AD<14>" IOSTANDARD = PCI33_5;
>> NET "AD<13>" LOC = "P31" ;
>> NET "AD<13>" IOSTANDARD = PCI33_5;
>> NET "AD<12>" LOC = "P33" ;
>> NET "AD<12>" IOSTANDARD = PCI33_5;
>> NET "AD<11>" LOC = "P34" ;
>> NET "AD<11>" IOSTANDARD = PCI33_5;
>> NET "AD<10>" LOC = "P35" ;
>> NET "AD<10>" IOSTANDARD = PCI33_5;
>> NET "AD<9>" LOC = "P36" ;
>> NET "AD<9>" IOSTANDARD = PCI33_5;
>> NET "AD<8>" LOC = "P41" ;
>> NET "AD<8>" IOSTANDARD = PCI33_5;
>> NET "AD<7>" LOC = "P42" ;
>> NET "AD<7>" IOSTANDARD = PCI33_5;
>> NET "AD<6>" LOC = "P43" ;
>> NET "AD<6>" IOSTANDARD = PCI33_5;
>> NET "AD<5>" LOC = "P44" ;
>> NET "AD<5>" IOSTANDARD = PCI33_5;
>> NET "AD<4>" LOC = "P45" ;
>> NET "AD<4>" IOSTANDARD = PCI33_5;
>> NET "AD<3>" LOC = "P46" ;
>> NET "AD<3>" IOSTANDARD = PCI33_5;
>> NET "AD<2>" LOC = "P47" ;
>> NET "AD<2>" IOSTANDARD = PCI33_5;
>> NET "AD<1>" LOC = "P48" ;
>> NET "AD<1>" IOSTANDARD = PCI33_5;
>> NET "AD<0>" LOC = "P49" ;
>> NET "AD<0>" IOSTANDARD = PCI33_5;
>> NET "ACK_O" LOC = "P90" ;
>>
>
>
>--
>To unsubscribe from pci mailing list please visit
http://www.opencores.org/mailinglists.shtml
__________________________________
Nico Weling
System Designer
Ericsson Eurolab Deutschland GmbH
Verification Tool Design
Tel: +49 2407 575 5217
Fax: +49 2407 575 651
Dect:+49 2407 575 89339
mailto:Nico.Weling@eed.ericsson.se
__________________________________
VERSION 6
BEGIN SCHEMATIC
BEGIN ATTR DeviceFamilyName "spartan2"
DELETE all:0
EDITNAME all:0
EDITTRAIT all:0
END ATTR
BEGIN NETLIST
SIGNAL "CLK_I"
SIGNAL "CLK"
SIGNAL "GNT"
SIGNAL "IDSEL"
SIGNAL "INT_I"
SIGNAL "CYC_I"
SIGNAL "STB_I"
SIGNAL "WE_I"
SIGNAL "CAB_I"
SIGNAL "RTY_I"
SIGNAL "ERR_I"
SIGNAL "ADR_I(7:0)"
SIGNAL "SEL_I(3:0)"
SIGNAL "REQ"
SIGNAL "SERR"
BEGIN SIGNAL "RST_O"
END SIGNAL
SIGNAL "INT_O"
SIGNAL "ACK_O"
SIGNAL "RTY_O"
SIGNAL "ERR_O"
SIGNAL "CYC_O"
SIGNAL "CAB_O"
SIGNAL "SDAT_O(7:0)"
SIGNAL "ADR_O(7:0)"
SIGNAL "SEL_O(3:0)"
SIGNAL "RST"
SIGNAL "INTA"
SIGNAL "FRAME"
SIGNAL "IRDY"
SIGNAL "DEVSEL"
SIGNAL "TRDY"
SIGNAL "STOP"
SIGNAL "PAR"
SIGNAL "PERR"
SIGNAL "AD(31:0)"
SIGNAL "CBE(3:0)"
SIGNAL "SDAT_I(7:0)"
SIGNAL "MDAT_I(7:0)"
SIGNAL "XLXN_127"
SIGNAL "XLXN_1"
SIGNAL "XLXN_138"
SIGNAL "PRT_O(7:0)"
SIGNAL "XLXN_145"
SIGNAL "XLXN_146"
SIGNAL "XLXN_148"
SIGNAL "XLXN_149"
SIGNAL "XLXN_150"
SIGNAL "XLXN_151"
SIGNAL "XLXN_153(7:0)"
PORT Input "CLK_I"
PORT Input "CLK"
PORT Input "GNT"
PORT Input "IDSEL"
PORT Input "INT_I"
PORT Input "CYC_I"
PORT Input "STB_I"
PORT Input "WE_I"
PORT Input "CAB_I"
PORT Input "RTY_I"
PORT Input "ERR_I"
PORT Input "ADR_I(7:0)"
PORT Input "SEL_I(3:0)"
PORT Output "REQ"
PORT Output "SERR"
PORT Output "INT_O"
PORT Output "ACK_O"
PORT Output "RTY_O"
PORT Output "ERR_O"
PORT Output "CYC_O"
PORT Output "CAB_O"
PORT Output "SDAT_O(7:0)"
PORT Output "ADR_O(7:0)"
PORT Output "SEL_O(3:0)"
PORT Output "RST"
PORT Output "INTA"
PORT Output "FRAME"
PORT Output "IRDY"
PORT Output "DEVSEL"
PORT Output "TRDY"
PORT Output "STOP"
PORT Output "PAR"
PORT Output "PERR"
PORT Output "AD(31:0)"
PORT Output "CBE(3:0)"
PORT Input "SDAT_I(7:0)"
PORT Input "MDAT_I(7:0)"
PORT Output "PRT_O(7:0)"
BEGIN BLOCKDEF "top"
TIMESTAMP 2003 6 14 1 52 44
RECTANGLE N 64 -1664 464 0
LINE N 64 -1632 0 -1632
LINE N 64 -1536 0 -1536
LINE N 64 -1440 0 -1440
LINE N 64 -1344 0 -1344
LINE N 64 -1248 0 -1248
LINE N 64 -1152 0 -1152
LINE N 64 -1056 0 -1056
LINE N 64 -960 0 -960
LINE N 64 -864 0 -864
LINE N 64 -768 0 -768
LINE N 64 -672 0 -672
LINE N 64 -576 0 -576
LINE N 64 -480 0 -480
LINE N 64 -384 0 -384
RECTANGLE N 0 -396 64 -372
LINE N 64 -288 0 -288
RECTANGLE N 0 -300 64 -276
LINE N 64 -192 0 -192
RECTANGLE N 0 -204 64 -180
LINE N 64 -96 0 -96
RECTANGLE N 0 -108 64 -84
LINE N 464 -1632 528 -1632
LINE N 464 -1568 528 -1568
LINE N 464 -1504 528 -1504
LINE N 464 -1440 528 -1440
LINE N 464 -1376 528 -1376
LINE N 464 -1312 528 -1312
LINE N 464 -1248 528 -1248
LINE N 464 -1184 528 -1184
LINE N 464 -1120 528 -1120
LINE N 464 -1056 528 -1056
LINE N 464 -992 528 -992
LINE N 464 -928 528 -928
RECTANGLE N 464 -940 528 -916
LINE N 464 -864 528 -864
RECTANGLE N 464 -876 528 -852
LINE N 464 -800 528 -800
RECTANGLE N 464 -812 528 -788
LINE N 464 -736 528 -736
RECTANGLE N 464 -748 528 -724
LINE N 464 -672 528 -672
LINE N 464 -608 528 -608
LINE N 464 -544 528 -544
LINE N 464 -480 528 -480
LINE N 464 -416 528 -416
LINE N 464 -352 528 -352
LINE N 464 -288 528 -288
LINE N 464 -224 528 -224
LINE N 464 -160 528 -160
LINE N 464 -96 528 -96
RECTANGLE N 464 -108 528 -84
LINE N 464 -32 528 -32
RECTANGLE N 464 -44 528 -20
END BLOCKDEF
BEGIN BLOCKDEF "buf"
TIMESTAMP 2001 2 2 12 51 12
LINE N 0 -32 64 -32
LINE N 224 -32 128 -32
LINE N 64 0 128 -32
LINE N 128 -32 64 -64
LINE N 64 -64 64 0
END BLOCKDEF
BEGIN BLOCKDEF "and2"
TIMESTAMP 2001 2 2 12 53 52
LINE N 0 -64 64 -64
LINE N 0 -128 64 -128
LINE N 256 -96 192 -96
ARC N 96 -144 192 -48 144 -48 144 -144
LINE N 144 -48 64 -48
LINE N 64 -144 144 -144
LINE N 64 -48 64 -144
END BLOCKDEF
BEGIN BLOCKDEF "fd8ce"
TIMESTAMP 2001 2 2 12 52 25
LINE N 0 -128 64 -128
LINE N 0 -192 64 -192
LINE N 0 -32 64 -32
LINE N 0 -256 64 -256
LINE N 384 -256 320 -256
LINE N 192 -32 64 -32
LINE N 192 -64 192 -32
LINE N 80 -128 64 -144
LINE N 64 -112 80 -128
RECTANGLE N 320 -268 384 -244
RECTANGLE N 0 -268 64 -244
RECTANGLE N 64 -320 320 -64
END BLOCKDEF
BEGIN BLOCK "XLXI_1" "top"
PIN "CLK" "CLK"
PIN "GNT" "GNT"
PIN "IDSEL" "IDSEL"
PIN "CLK_I" "CLK_I"
PIN "RST_I"
PIN "INT_I" "INT_I"
PIN "CYC_I" "CYC_I"
PIN "STB_I" "STB_I"
PIN "WE_I" "WE_I"
PIN "CAB_I" "CAB_I"
PIN "ACK_I" "XLXN_151"
PIN "RTY_I" "RTY_I"
PIN "ERR_I" "ERR_I"
PIN "ADR_I(7:0)" "ADR_I(7:0)"
PIN "SDAT_I(7:0)" "SDAT_I(7:0)"
PIN "SEL_I(3:0)" "SEL_I(3:0)"
PIN "MDAT_I(7:0)" "MDAT_I(7:0)"
PIN "RST" "RST"
PIN "INTA" "INTA"
PIN "FRAME" "FRAME"
PIN "IRDY" "IRDY"
PIN "DEVSEL" "DEVSEL"
PIN "TRDY" "TRDY"
PIN "STOP" "STOP"
PIN "PAR" "PAR"
PIN "PERR" "PERR"
PIN "AD(31:0)" "AD(31:0)"
PIN "CBE(3:0)" "CBE(3:0)"
PIN "REQ" "REQ"
PIN "SERR" "SERR"
PIN "RST_O" "RST_O"
PIN "INT_O" "INT_O"
PIN "ACK_O" "ACK_O"
PIN "RTY_O" "RTY_O"
PIN "ERR_O" "ERR_O"
PIN "CYC_O" "CYC_O"
PIN "STB_O" "XLXN_150"
PIN "WE_O" "XLXN_146"
PIN "CAB_O" "CAB_O"
PIN "SDAT_O(7:0)" "SDAT_O(7:0)"
PIN "ADR_O(7:0)" "ADR_O(7:0)"
PIN "MDAT_O(7:0)" "XLXN_153(7:0)"
PIN "SEL_O(3:0)" "SEL_O(3:0)"
END BLOCK
BEGIN BLOCK "XLXI_2" "and2"
PIN "I0" "XLXN_146"
PIN "I1" "XLXN_150"
PIN "O" "XLXN_1"
END BLOCK
BEGIN BLOCK "XLXI_34" "buf"
PIN "I" "XLXN_150"
PIN "O" "XLXN_151"
END BLOCK
BEGIN BLOCK "XLXI_6" "fd8ce"
PIN "C" "CLK_I"
PIN "CE" "XLXN_1"
PIN "CLR" "RST_O"
PIN "D(7:0)" "XLXN_153(7:0)"
PIN "Q(7:0)" "PRT_O(7:0)"
END BLOCK
END NETLIST
BEGIN SHEET 1 3801 2688
ATTR LengthUnitName "CM"
ATTR GridsPerUnit "4"
BEGIN INSTANCE "XLXI_1" 1040 2080 R0
END INSTANCE
BEGIN DISPLAY 1132 268 TEXT "WB MASTER"
FONT 60 "Arial"
END DISPLAY
BEGIN BRANCH "CLK_I"
WIRE 480 320 976 320
WIRE 976 320 976 736
WIRE 976 736 1040 736
WIRE 976 320 1840 320
WIRE 1840 320 1840 1408
WIRE 1840 1408 2896 1408
END BRANCH
IOMARKER 480 320 "CLK_I" R180 28
BEGIN DISPLAY 304 256 TEXT SYSCON
FONT 60 "Arial"
END DISPLAY
BEGIN BRANCH "CLK"
WIRE 896 448 1040 448
END BRANCH
BEGIN BRANCH "GNT"
WIRE 896 544 1040 544
END BRANCH
BEGIN BRANCH "IDSEL"
WIRE 896 640 1040 640
END BRANCH
BEGIN BRANCH "INT_I"
WIRE 896 928 1040 928
END BRANCH
BEGIN BRANCH "CYC_I"
WIRE 896 1024 1040 1024
END BRANCH
BEGIN BRANCH "STB_I"
WIRE 896 1120 1040 1120
END BRANCH
BEGIN BRANCH "WE_I"
WIRE 896 1216 1040 1216
END BRANCH
BEGIN BRANCH "CAB_I"
WIRE 896 1312 1040 1312
END BRANCH
BEGIN BRANCH "RTY_I"
WIRE 896 1504 1040 1504
END BRANCH
BEGIN BRANCH "ERR_I"
WIRE 896 1600 1040 1600
END BRANCH
BEGIN BRANCH "ADR_I(7:0)"
WIRE 896 1696 1040 1696
END BRANCH
BEGIN BRANCH "SEL_I(3:0)"
WIRE 880 1888 1040 1888
END BRANCH
BEGIN BRANCH "REQ"
WIRE 1568 448 1600 448
END BRANCH
BEGIN BRANCH "SERR"
WIRE 1568 512 1600 512
END BRANCH
BEGIN BRANCH "RST_O"
WIRE 1568 576 2496 576
WIRE 2496 576 2496 1504
WIRE 2496 1504 2896 1504
END BRANCH
BEGIN BRANCH "INT_O"
WIRE 1568 640 1600 640
END BRANCH
BEGIN BRANCH "ACK_O"
WIRE 1568 704 1600 704
END BRANCH
BEGIN BRANCH "RTY_O"
WIRE 1568 768 1600 768
END BRANCH
BEGIN BRANCH "ERR_O"
WIRE 1568 832 1600 832
END BRANCH
BEGIN BRANCH "CYC_O"
WIRE 1568 896 1600 896
END BRANCH
BEGIN BRANCH "CAB_O"
WIRE 1568 1088 1600 1088
END BRANCH
BEGIN BRANCH "SDAT_O(7:0)"
WIRE 1568 1152 1600 1152
END BRANCH
BEGIN BRANCH "ADR_O(7:0)"
WIRE 1568 1216 1600 1216
END BRANCH
BEGIN BRANCH "SEL_O(3:0)"
WIRE 1568 1344 1600 1344
END BRANCH
BEGIN BRANCH "RST"
WIRE 1568 1408 1600 1408
END BRANCH
BEGIN BRANCH "INTA"
WIRE 1568 1472 1600 1472
END BRANCH
BEGIN BRANCH "FRAME"
WIRE 1568 1536 1600 1536
END BRANCH
BEGIN BRANCH "IRDY"
WIRE 1568 1600 1600 1600
END BRANCH
BEGIN BRANCH "DEVSEL"
WIRE 1568 1664 1600 1664
END BRANCH
BEGIN BRANCH "TRDY"
WIRE 1568 1728 1600 1728
END BRANCH
BEGIN BRANCH "STOP"
WIRE 1568 1792 1600 1792
END BRANCH
BEGIN BRANCH "PAR"
WIRE 1568 1856 1600 1856
END BRANCH
BEGIN BRANCH "PERR"
WIRE 1568 1920 1600 1920
END BRANCH
BEGIN BRANCH "AD(31:0)"
WIRE 1568 1984 1600 1984
END BRANCH
BEGIN BRANCH "CBE(3:0)"
WIRE 1568 2048 1600 2048
END BRANCH
IOMARKER 880 1888 "SEL_I(3:0)" R180 28
IOMARKER 896 1696 "ADR_I(7:0)" R180 28
IOMARKER 896 1600 "ERR_I" R180 28
IOMARKER 896 1504 "RTY_I" R180 28
IOMARKER 896 1312 "CAB_I" R180 28
IOMARKER 896 1216 "WE_I" R180 28
IOMARKER 896 1120 "STB_I" R180 28
IOMARKER 896 1024 "CYC_I" R180 28
IOMARKER 896 448 "CLK" R180 28
IOMARKER 896 544 "GNT" R180 28
IOMARKER 896 640 "IDSEL" R180 28
IOMARKER 896 928 "INT_I" R180 28
IOMARKER 1600 448 "REQ" R0 28
IOMARKER 1600 512 "SERR" R0 28
IOMARKER 1600 640 "INT_O" R0 28
IOMARKER 1600 704 "ACK_O" R0 28
IOMARKER 1600 768 "RTY_O" R0 28
IOMARKER 1600 832 "ERR_O" R0 28
IOMARKER 1600 896 "CYC_O" R0 28
IOMARKER 1600 1088 "CAB_O" R0 28
IOMARKER 1600 1152 "SDAT_O(7:0)" R0 28
IOMARKER 1600 1216 "ADR_O(7:0)" R0 28
IOMARKER 1600 1344 "SEL_O(3:0)" R0 28
IOMARKER 1600 1408 "RST" R0 28
IOMARKER 1600 1472 "INTA" R0 28
IOMARKER 1600 1536 "FRAME" R0 28
IOMARKER 1600 1600 "IRDY" R0 28
IOMARKER 1600 1664 "DEVSEL" R0 28
IOMARKER 1600 1728 "TRDY" R0 28
IOMARKER 1600 1792 "STOP" R0 28
IOMARKER 1600 1856 "PAR" R0 28
IOMARKER 1600 1920 "PERR" R0 28
IOMARKER 1600 1984 "AD(31:0)" R0 28
IOMARKER 1600 2048 "CBE(3:0)" R0 28
BEGIN BRANCH "SDAT_I(7:0)"
WIRE 896 1792 1040 1792
END BRANCH
IOMARKER 896 1792 "SDAT_I(7:0)" R180 28
BEGIN BRANCH "MDAT_I(7:0)"
WIRE 896 1984 1040 1984
END BRANCH
IOMARKER 896 1984 "MDAT_I(7:0)" R180 28
BEGIN BRANCH "XLXN_1"
WIRE 2496 1344 2896 1344
END BRANCH
INSTANCE "XLXI_6" 2896 1536 R0
BEGIN BRANCH "PRT_O(7:0)"
WIRE 3280 1280 3408 1280
END BRANCH
IOMARKER 3408 1280 "PRT_O(7:0)" R0 28
BEGIN DISPLAY 2604 1240 TEXT DAT_I(7..0)
FONT 48 "Arial"
END DISPLAY
BEGIN DISPLAY 2588 1480 TEXT RST_I
FONT 48 "Arial"
END DISPLAY
INSTANCE "XLXI_2" 2240 1440 R0
BEGIN BRANCH "XLXN_146"
WIRE 1568 1024 1872 1024
WIRE 1872 1024 1872 1376
WIRE 1872 1376 2240 1376
END BRANCH
BEGIN DISPLAY 2064 1348 TEXT WE_I
FONT 48 "Arial"
END DISPLAY
BEGIN DISPLAY 2572 1380 TEXT CLK_I
FONT 48 "Arial"
END DISPLAY
BEGIN DISPLAY 2060 1284 TEXT STB_I
FONT 48 "Arial"
END DISPLAY
BEGIN BRANCH "XLXN_150"
WIRE 1568 960 1904 960
WIRE 1904 960 1904 1312
WIRE 1904 1312 2208 1312
WIRE 2208 1312 2240 1312
WIRE 2208 1312 2208 2144
WIRE 2080 2144 2208 2144
END BRANCH
INSTANCE "XLXI_34" 2080 2112 R180
BEGIN DISPLAY 2048 2112 TEXT ACK_O
FONT 48 "Arial"
END DISPLAY
BEGIN BRANCH "XLXN_151"
WIRE 992 1408 1040 1408
WIRE 992 1408 992 2144
WIRE 992 2144 1856 2144
END BRANCH
BEGIN BRANCH "XLXN_153(7:0)"
WIRE 1568 1280 1968 1280
WIRE 1968 1248 1968 1280
WIRE 1968 1248 2560 1248
WIRE 2560 1248 2560 1280
WIRE 2560 1280 2896 1280
END BRANCH
BEGIN DISPLAY 2564 1044 TEXT "WB SLAVE (IO 8 bit)"
FONT 60 "Arial"
END DISPLAY
END SHEET
END SCHEMATIC