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Re: [pci] RST_I net missing?
Hi!
If you are using GUEST implementation of the bridge, RST_I is not connected
anywhere.
I guess the synthesis optimizes it away, and then the constraint is no
longer valid.
About the warnings - I can see the compiler is complaining about
redefinition of the defines.
It looks like the defines are treated as global, which should not be the
case.
I can see that the first file is compiled without warnings, all the others,
which include the pci_constants.v, produce a lot of warnings.
I would say this is nothing to worry about.
Regards,
Miha Dolenc
----- Original Message -----
From: "Nico Weling" <eedniwe@eed.ericsson.se>
To: <pci@opencores.org>
Sent: Friday, June 20, 2003 9:47 AM
Subject: [pci] RST_I net missing?
> Hi,
>
> I'm using the TOP.v file of the pci_bridge only (no CRT application)
>
> If I create an constrains file in which I connect only all PCI related
pins I
> can successfully generate a working bit file.
>
> But if I, in addition to the previous ucf-file, connect RST_I net to an
physical
> pin I get the following error message:
>
>
============================================================================
====
> ERROR:NgdBuild:755 - Line 10 in 'aimsblaster4wbm_io8.ucf': Could not find
net(s)
>
> 'RST_I' in the design. To suppress this error use the -aul switch,
specify
> the correct net name or remove the constraint.
>
============================================================================
====
>
> TOP.v:
> --------------------------------
> ...
> module TOP
> (
> ...
> RST_I,
> ...
>
> // WISHBONE system signals
> ...
> input RST_I ;
> ...
> --------------------------------
>
> Attached is my .ucf file. Does someone see what I did wrong?
>
> Regards/Nico.
>
>
> PS: I changed the ucf file using "Xininx PACE" and there RST_I was in the
list
> of IO's.
>
>
> __________________________________
> Nico Weling
> System Designer
> Ericsson Eurolab Deutschland GmbH
> Verification Tool Design
>
> Tel: +49 2407 575 5217
> Fax: +49 2407 575 651
> Dect:+49 2407 575 89339
> mailto:Nico.Weling@eed.ericsson.se
> __________________________________
>
>
----------------------------------------------------------------------------
----
> #PACE: Start of Constraints extracted by PACE from the Design
> NET "WE_O" LOC = "P84" ;
> NET "TRDY" LOC = "P18" ;
> NET "TRDY" IOSTANDARD = PCI33_5;
> NET "STOP" LOC = "P21" ;
> NET "STOP" IOSTANDARD = PCI33_5;
> NET "STB_O" LOC = "P95" ;
> NET "SERR" LOC = "P23" ;
> NET "SERR" IOSTANDARD = PCI33_5;
> NET "RST_I" LOC = "P149" ;
> NET "RST_I" IOSTANDARD = LVTTL;
> NET "RST" LOC = "P192" ;
> NET "RST" IOSTANDARD = PCI33_5;
> NET "REQ" LOC = "P194" ;
> NET "REQ" IOSTANDARD = PCI33_5;
> NET "PERR" LOC = "P22" ;
> NET "PERR" IOSTANDARD = PCI33_5;
> NET "PAR" LOC = "P24" ;
> NET "PAR" IOSTANDARD = PCI33_5;
> NET "MDAT_O<7>" LOC = "P98" ;
> NET "MDAT_O<6>" LOC = "P100" ;
> NET "MDAT_O<5>" LOC = "P94" ;
> NET "MDAT_O<4>" LOC = "P96" ;
> NET "MDAT_O<3>" LOC = "P97" ;
> NET "MDAT_O<2>" LOC = "P99" ;
> NET "MDAT_O<1>" LOC = "P101" ;
> NET "MDAT_O<0>" LOC = "P102" ;
> NET "IRDY" LOC = "P17" ;
> NET "IRDY" IOSTANDARD = PCI33_5;
> NET "INT_I" LOC = "P58" ;
> NET "INTA" LOC = "P191" ;
> NET "INTA" IOSTANDARD = PCI33_5;
> NET "IDSEL" LOC = "P3" ;
> NET "IDSEL" IOSTANDARD = PCI33_5;
> NET "GNT" LOC = "P193" ;
> NET "GNT" IOSTANDARD = PCI33_5;
> NET "FRAME" LOC = "P16" ;
> NET "FRAME" IOSTANDARD = PCI33_5;
> NET "DEVSEL" LOC = "P20" ;
> NET "DEVSEL" IOSTANDARD = PCI33_5;
> NET "CLK_I" LOC = "P77" ;
> NET "CLK" LOC = "P185" ;
> NET "CLK" IOSTANDARD = PCI33_5;
> NET "CBE<3>" LOC = "P199" ;
> NET "CBE<3>" IOSTANDARD = PCI33_5;
> NET "CBE<2>" LOC = "P15" ;
> NET "CBE<2>" IOSTANDARD = PCI33_5;
> NET "CBE<1>" LOC = "P27" ;
> NET "CBE<1>" IOSTANDARD = PCI33_5;
> NET "CBE<0>" LOC = "P37" ;
> NET "CBE<0>" IOSTANDARD = PCI33_5;
> NET "AD<31>" LOC = "P195" ;
> NET "AD<31>" IOSTANDARD = PCI33_5;
> NET "AD<30>" LOC = "P200" ;
> NET "AD<30>" IOSTANDARD = PCI33_5;
> NET "AD<29>" LOC = "P201" ;
> NET "AD<29>" IOSTANDARD = PCI33_5;
> NET "AD<28>" LOC = "P202" ;
> NET "AD<28>" IOSTANDARD = PCI33_5;
> NET "AD<27>" LOC = "P203" ;
> NET "AD<27>" IOSTANDARD = PCI33_5;
> NET "AD<26>" LOC = "P204" ;
> NET "AD<26>" IOSTANDARD = PCI33_5;
> NET "AD<25>" LOC = "P205" ;
> NET "AD<25>" IOSTANDARD = PCI33_5;
> NET "AD<24>" LOC = "P206" ;
> NET "AD<24>" IOSTANDARD = PCI33_5;
> NET "AD<23>" LOC = "P4" ;
> NET "AD<23>" IOSTANDARD = PCI33_5;
> NET "AD<22>" LOC = "P5" ;
> NET "AD<22>" IOSTANDARD = PCI33_5;
> NET "AD<21>" LOC = "P6" ;
> NET "AD<21>" IOSTANDARD = PCI33_5;
> NET "AD<20>" LOC = "P7" ;
> NET "AD<20>" IOSTANDARD = PCI33_5;
> NET "AD<19>" LOC = "P8" ;
> NET "AD<19>" IOSTANDARD = PCI33_5;
> NET "AD<18>" LOC = "P9" ;
> NET "AD<18>" IOSTANDARD = PCI33_5;
> NET "AD<17>" LOC = "P10" ;
> NET "AD<17>" IOSTANDARD = PCI33_5;
> NET "AD<16>" LOC = "P14" ;
> NET "AD<16>" IOSTANDARD = PCI33_5;
> NET "AD<15>" LOC = "P29" ;
> NET "AD<15>" IOSTANDARD = PCI33_5;
> NET "AD<14>" LOC = "P30" ;
> NET "AD<14>" IOSTANDARD = PCI33_5;
> NET "AD<13>" LOC = "P31" ;
> NET "AD<13>" IOSTANDARD = PCI33_5;
> NET "AD<12>" LOC = "P33" ;
> NET "AD<12>" IOSTANDARD = PCI33_5;
> NET "AD<11>" LOC = "P34" ;
> NET "AD<11>" IOSTANDARD = PCI33_5;
> NET "AD<10>" LOC = "P35" ;
> NET "AD<10>" IOSTANDARD = PCI33_5;
> NET "AD<9>" LOC = "P36" ;
> NET "AD<9>" IOSTANDARD = PCI33_5;
> NET "AD<8>" LOC = "P41" ;
> NET "AD<8>" IOSTANDARD = PCI33_5;
> NET "AD<7>" LOC = "P42" ;
> NET "AD<7>" IOSTANDARD = PCI33_5;
> NET "AD<6>" LOC = "P43" ;
> NET "AD<6>" IOSTANDARD = PCI33_5;
> NET "AD<5>" LOC = "P44" ;
> NET "AD<5>" IOSTANDARD = PCI33_5;
> NET "AD<4>" LOC = "P45" ;
> NET "AD<4>" IOSTANDARD = PCI33_5;
> NET "AD<3>" LOC = "P46" ;
> NET "AD<3>" IOSTANDARD = PCI33_5;
> NET "AD<2>" LOC = "P47" ;
> NET "AD<2>" IOSTANDARD = PCI33_5;
> NET "AD<1>" LOC = "P48" ;
> NET "AD<1>" IOSTANDARD = PCI33_5;
> NET "AD<0>" LOC = "P49" ;
> NET "AD<0>" IOSTANDARD = PCI33_5;
> NET "ACK_O" LOC = "P90" ;
>
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