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[pci] prob wif PCI ip core app's ucf file
Hi,
I am using the ISE Webpack 5.1i to run the PCi IP core. The target
device is a Spartan II FPGA (device xc2s150, package pq208, speed -5)
The sysnthesis of the pci bridge application (crt thingy) was successful
abeit loads of warnings. However, the translation process produced
some errors which i could not resolve:
ERROR:NgdBuild:753 - Line 550 in 'pci_crt.ucf': Could not find instance(s)
'bridge/pci_io_mux/ad_iob0/dat_out_reg' in the design. To suppress this
error specify the correct instance name or remove the constraint.
ERROR:NgdBuild:753 - Line 551 in 'pci_crt.ucf': Could not find instance(s)
'bridge/pci_io_mux/ad_iob1/dat_out_reg' in the design. To suppress this
error specify the correct instance name or remove the constraint.
...
The same error goes for all the instances after line 550 in the constraint
file. Any idea why these errors occur?
I tried removing all the instances after line 550 and i could pass the
translation process but it will get me as far as Place and Route. At
PAR, i will encounter timing errors as follow:
Asterisk (*) preceding a constraint indicates it was not met.
----------------------------------------------------------------------
Constraint | Requested | Actual | Logic
| | | Levels
----------------------------------------------------------------------
TS_CLK = PERIOD TIMEGRP "CLK" 30 nS HI | 30.000ns | 8.984ns| 17
GH 50.000000 % | | |
----------------------------------------------------------------------
TS_CRT_CLK = PERIOD TIMEGRP "CRT_CLK" 44 | 44.000ns|11.260ns|8
nS HIGH 50.000000 % | | |
----------------------------------------------------------------------
*TS_CLK_2_CRT_CLK=MAXDELAY FROM TIMEGRP|5.000ns|11.560ns|8
"CLK" TO TIMEGRP "CRT_CLK" 5 nS | | |
----------------------------------------------------------------------
* TS_CRT_CLK_2_CLK=MAXDELAY FROM TIMEGRP| 5.000ns|7.613ns|5
"CRT_CLK" TO TIMEGRP "CLK" 5 nS | | |
----------------------------------------------------------------------
COMP "IDSEL" OFFSET = IN 7 nS BEFORE COM |7.000ns|2.772ns | 1
P "CLK" | | |
----------------------------------------------------------------------
COMP "GNT" OFFSET =IN 10 nS BEFORE COMP|10.000ns|4.077ns| 5
"CLK" | | |
----------------------------------------------------------------------
COMP "STOP" OFFSET = IN 7 nS BEFORE COMP|7.000ns|3.346ns | 5
"CLK" | | |
----------------------------------------------------------------------
COMP "STOP" OFFSET=OUT 11 nS AFTER COM|11.000ns|10.556ns|1
P "CLK" | | |
----------------------------------------------------------------------
COMP "DEVSEL" OFFSET = IN 7 nS BEFORE CO |7.000ns|2.772ns| 1
MP "CLK" | | |
----------------------------------------------------------------------
COMP "DEVSEL" OFFSET=OUT 11 nS AFTER C |11.000ns|10.556ns|1
OMP "CLK" | | |
----------------------------------------------------------------------
COMP "IRDY" OFFSET = IN 7 nS BEFORE COMP|7.000ns | 3.565ns| 4
"CLK" | | |
----------------------------------------------------------------------
COMP "IRDY" OFFSET =OUT 11 nS AFTER COM|11.000ns|9.422ns| 0
P "CLK" | | |
----------------------------------------------------------------------
COMP "TRDY" OFFSET =IN 7 nS BEFORE COMP|7.000ns|3.346ns| 5
"CLK" | | |
----------------------------------------------------------------------
*COMP "TRDY" OFFSET=OUT 10 nS AFTER COM|10.000ns|10.556ns|1
P "CLK" | | |
----------------------------------------------------------------------
COMP "PERR" OFFSET = IN 7 nS BEFORE COMP |7.000ns|0.721ns| 2
"CLK" | | |
----------------------------------------------------------------------
COMP "PERR" OFFSET =OUT 11 nS AFTER COM|11.000ns|9.422ns| 0
P "CLK" | | |
----------------------------------------------------------------------
COMP "PAR" OFFSET =IN 7 nS BEFORE COMP | 7.000ns| 1.452ns| 2
"CLK" | | |
----------------------------------------------------------------------
COMP "PAR" OFFSET=OUT 11 nS AFTER COMP|11.000ns|9.422ns| 0
"CLK" | | |
----------------------------------------------------------------------
COMP "FRAME" OFFSET =IN 7 nS BEFORE COM|7.000ns|3.565ns| 4
P "CLK" | | |
----------------------------------------------------------------------
COMP "FRAME" OFFSET=OUT 11 nS AFTER CO|11.000ns|9.422ns| 0
MP "CLK" | | |
----------------------------------------------------------------------
COMP "SERR" OFFSET=OUT 11 nS AFTER COM|11.000ns|9.422ns| 0
P "CLK" | | |
----------------------------------------------------------------------
COMP "REQ" OFFSET=OUT 12 nS AFTER COMP|12.000ns|9.422ns| 0
"CLK" | | |
----------------------------------------------------------------------
TIMEGRP "PCI_AD" OFFSET = IN 7 nS BEFORE | 7.000ns| 2.772ns| 1
COMP "CLK" | | |
----------------------------------------------------------------------
TIMEGRP "PCI_AD" OFFSET=OUT 11 nS AFTE|11.000ns|10.556ns| 1
R COMP "CLK" | | |
----------------------------------------------------------------------
TIMEGRP "PCI_CBE" OFFSET = IN 7 nS BEFOR| 7.000ns| 2.772ns | 1
E COMP "CLK" | | |
----------------------------------------------------------------------
TIMEGRP "PCI_CBE" OFFSET=OUT 11 nS AFT|11.000ns|10.556ns| 1
ER COMP "CLK" | | |
----------------------------------------------------------------------
3 constraints not met.
ERROR: PAR failed
However, when i set the PAR tool to ignore timing contraints, the PAR
will run to completion successfully abeit a few warnings.
Then again, there's a concern that the design ultilisation differs frm the
log file generated by the author of the PCI bridge..
The following is the summary of my device ultilisation:
Number of External GCLKIOBs 2 out of 4 50%
Number of External IOBs 64 out of 140 45%
Number of LOCed External IOBs 64 out of 64 100%
Number of BLOCKRAMs 6 out of 12 50%
Number of SLICEs 1370 out of 1728 79%
Number of GCLKs 2 out of 4 50%
The following is the summary of device implementation i that was logged
in fe.log that i downloaded frm pci\apps\crt\syn\out on the open core
server:
Device utilization summary:
Number of External GCLKIOBs 2 out of 4 50%
Number of External IOBs 64 out of 140 45%
Number of BLOCKRAMs 6 out of 12 50%
Number of SLICEs 1402 out of 1728 81%
Number of GCLKs 2 out of 4 50%
It seems that there's variance in the number of slices used. Please
advice. TIA.
Will
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