Re: [pci] Problem synthesizing PCI IP core

[Marco Buffa <marcobuffa@lombardiacom.it>]

* 31/12/02, 07:54, weiliang10@hotmail.com wrote:
> Error: syntax error at or near token 'tri0' 
> 
> which is basically in  line 83 of RAMB4_S16_S16.v (tri0 GSR = glbl.GSR;)
> 
> Any idea on how to overcome the problem?

Hi Will, I found a similar problem compiling the core.
Try to enable the "verilog preprocessor" in the synthesis' properties.

If you're using Xilinx ISE, more info at www.xilinx.com in the answer
database...

Bye.
-- 
Marco
 
"No, lo abbiamo esaminato dopo, e' perfetto.
Ma quando si ha paura si crede sempre che il motore vibri."
(Antoine de Saint-Exupery, "Volo di notte")
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