Re: [openrisc] is Cray needed to synthesize ORP

["Damjan Lampret" <lampret@opencores.org>]

Paul,

on 1GHz PIII with 1GB memory Synplify takes 1 hour to synthesize it. You
must be synthsizing the "simulation" version. In the mem_if you have large
chunks of memory that is only used for simulation. The memory models are
there to simulate zero delay memories (which is not possible with mem_if if
mekory models are "external" to the orp_soc). So if you take simulation
configuration of the orp_soc, it will try to synthesize several million
flops as RAM.

In general, folks, look at what you are synthesizing. This sin't meant to be
"plug the files into synthesis tool and you will get your PC out of it".
Remember OR1200 and perihperals used in orp_soc are targeted to ASIC, not
FPGA. FPGAs are merely to test stuff and as proof of concept. Real use of
the cores is in ASICs - read: silicon produced in multimillion olumes at
silicon foundries... You need at least 6+ months of experience doing
synthesis on other designs, or you will have to spend a few weeks to learn
it and break a few teeth before it will work for you. Considered you had
been warned.

regards,
Damjan

----- Original Message -----
From: "paul" <paulw@mmail.ath.cx>
To: <openrisc@opencores.org>
Sent: Saturday, June 21, 2003 8:13 AM
Subject: [openrisc] is Cray needed to synthesize ORP


> Hi
>
> Something is not right while I tried to synthesize ORP. My PC has 1.5G
> of memory and 1.7G AMD processor.
> It's been 24 hours. And it's still compiling... :) Status line showing
> "running verilog syntax check."
> Can someone give an example of how much CPU/Memory is needed and how
> much time it took?
>
> Thanks.
>
>
>
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