Re: [openrisc] orp_soc compilation problem

["Damjan Lampret" <lampret@opencores.org>]

Paul,

by reading OpenCores Guidelines you will find out that all synthesis scripts
should be in a directory called syn. Indeed there is directory syn directory
with two subdirectories. I assume you are not familiar with one of the
common FPGA synthesis tools called Synplicity Synplify Pro, because there is
a project file for Synplify Pro under orp_soc/syn/synplify and this project
file will load all RTL files.

There is orp_soc/README file that explains how to run simulation, and
simulation should be the first step to do. Once you ran simulation, you
should be familiar with or_soc to a point that synthezing it shouldn't be a
problem. You can then update the README file with instructions how to
perform synthesis.

regards,
Damjan

----- Original Message -----
From: "paul" <paulw@mmail.ath.cx>
To: <openrisc@opencores.org>
Sent: Thursday, June 05, 2003 12:11 PM
Subject: [openrisc] orp_soc compilation problem


> Hi
>
> I have this small problem. I have no idea what tool has been used to
> compile the orp_soc project.
> There is no document what so ever in the entire or1k CVS. There is also
> no document even to briefly describe the hierarchy of the folders.
>
> I am under "or1k/orp/orp_soc/rtl/verilog" and can see 4 top files:
> tc_top.v  tdm_slave_if.v  xsv_fpga_defines.v  xsv_fpga_top.v
> which is the top file?
>
> All there exist are specification documents, but what are sorely missing
> are implementation documents. There are no document that remotely
> describe what should be done with the source or how to configure it ,
> not to mention how to hack it. How would you expect the project to
> attract developers or even users ???
>
>
>
>
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