[openrisc] orp_soc compilation problem

[paul <paulw@mmail.ath.cx>]

Hi

I have this small problem. I have no idea what tool has been used to 
compile the orp_soc project.
There is no document what so ever in the entire or1k CVS. There is also 
no document even to briefly describe the hierarchy of the folders.

I am under "or1k/orp/orp_soc/rtl/verilog" and can see 4 top files: 
tc_top.v  tdm_slave_if.v  xsv_fpga_defines.v  xsv_fpga_top.v
which is the top file?

All there exist are specification documents, but what are sorely missing 
are implementation documents. There are no document that remotely 
describe what should be done with the source or how to configure it , 
not to mention how to hack it. How would you expect the project to 
attract developers or even users ???




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