Re: [openrisc] data cache and or1ksim

["xxxx" <meleth_esp@yahoo.es>]

Hi:

   When I use the stats command I obtain the number of misses. Using a
program with some memory access I obtain 0 hits and 0 misses in the data
cache. I activate it in the sim.cfg file and in the SPR. The only way I
obtain misses and hits are writing directly in memory using pointers. So I
suposse writes to stack are not cacheables, but these are quite ridiculous.

Thanks
----- Original Message -----
From: "Simon Srot" <simons@opencores.org>
To: <openrisc@opencores.org>
Sent: Monday, August 13, 2001 1:53 PM
Subject: Re: [openrisc] data cache and or1ksim


> Hi,
>
> I don't know exactly what you are talking about, but there is no
> difference between load/store operations that are used for accessing
> stack and load/store for everything else (there is only one set of
> load/store operations).
>
> Simon
>
> javier_castillo_villar@yahoo.es wrote:
> >
> > Hi:
> >
> >    I am simulating some programs over or1ksim and getting some results
> > about caches.
> > When I use a data cache I observe that memory operations against the
> > stack dont pass trough the cache.
> > Is this correct?
> > Since the compiler make all the oparations againts the stack whats the
> > sense of use a data cache?
> >
> > Thanks
> > --
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