Re: Re: Re: [openrisc] or1200 sim

[Damjan Lampret <lampret@opencores.org>]

On 02 May 2002 01:58 CET you wrote:

> 
> Hello, Damjan,
> 
> I'm still playing with the or1k simulation now. Since there is no flash.in 
> under or1k/orp/orp_soc/sim/src, I have tried to play with or1k/mp3 
> where there is a sample flash.in.

flash.in under or1k/mp3 has different memory scheme and it won't work under orp_soc.

> 
> By using ModelSim, I instantiated the top level module. When I tried to 
> run the design, there were two errors:
> "Error, two or more masters currently accessing FLASH"
> "Error, two or more masters currently accessing SRAM"
> and when I continue run the simulation, it is alway "HiZ" at "flash.d"
> Then what's possible source for the errors?

Wrong flash.in.

I have put some sample .mem files in the cvs (under http://www.opencores.org/cvsweb.shtml/or1k/orp/orp_soc/sim/src/). Just take the one you like and use it as flash.in.

> 
> As for the installation of or32-rtems-* tools, could you give me some 
> detailed instruction! I found it was not so straightforward.

On Linux box following http://www.opencores.org/projects/or1k/GNU Toolchain Port instructions should be straightforward. Can you please let me know exactly what kind of problems you have (output when trying to build the tools, log files etc). You can also try to build the or1ksim and run the testbench (do make under or1ksim/testbench).

regards,
Damjan

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