[openrisc] Re: PC as GPR?

[Andreas Bombe <bombe@informatik.tu-muenchen.de>]

On Wed, Mar 06, 2002 at 08:32:01PM -0800, Damjan Lampret wrote:
> I'd like to have very minimal set of instructions (integer) that allow
> building of very small and simple RISCs for use in FPGAs. That's why I think
> all the instructions that are only for performance optimizations, should be
> optional (or at least you can kick them out when you want to compile for
> small/simple RISC).

Fine, then define the instruction and let it trap and be software
implemented on simple implementations.  Seriously, function calls are
quite important and they shouldn't blow up code size immensely.

Even a software implemented multi register load/store would very likely be faster
than multiple load/store instructions since there is less pressure on
icache/itlb.  Besides, the cache is a not so simple performance
optimization itself, after all.

The purpose of a CPU is not to execute instructions as fast as possible,
it is to run software.  It shouldn't be fast but efficient.  There is a
balance to find between simplicity (hardware view) and usability
(software view).  Currently the hardware view is overrepresented.  Maybe
if I keep annoying you we will end up with something better :)

-- 
Andreas Bombe <bombe@informatik.tu-muenchen.de>    DSA key 0x04880A44
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