[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[cvs-checkins] Import

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] Import
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Thu, 21 Mar 2002 17:55:21 +0100
Sender: owner-cvs-checkins@opencores.org
CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	oc	02/03/21 17:55:20

Log message:
    First import of the "new" XESS XSV environment.
    
    Status:
    
    Vendor Tag:	dl
    Release Tags:	first
    
    N or1k/xess/xsv_fpga/verilog/xsv_fpga_top.v
    N or1k/xess/xsv_fpga/verilog/tdm_slave_if.v
    N or1k/xess/xsv_fpga/verilog/tc_top.v
    N or1k/xess/xsv_fpga/verilog/xsv_fpga_defines.v
    N or1k/xess/xsv_fpga/verilog/audio/audio_codec_if.v
    N or1k/xess/xsv_fpga/verilog/audio/audio_top.v
    N or1k/xess/xsv_fpga/verilog/audio/audio_wb_if.v
    N or1k/xess/xsv_fpga/verilog/audio/fifo_4095_16.v
    N or1k/xess/xsv_fpga/verilog/audio/fifo_empty_16.v
    N or1k/xess/xsv_fpga/verilog/dbg_interface/dbg_crc8_d1.v
    N or1k/xess/xsv_fpga/verilog/dbg_interface/dbg_defines.v
    N or1k/xess/xsv_fpga/verilog/dbg_interface/dbg_register.v
    N or1k/xess/xsv_fpga/verilog/dbg_interface/dbg_registers.v
    N or1k/xess/xsv_fpga/verilog/dbg_interface/dbg_sync_clk1_clk2.v
    N or1k/xess/xsv_fpga/verilog/dbg_interface/dbg_top.v
    N or1k/xess/xsv_fpga/verilog/dbg_interface/dbg_trace.v
    N or1k/xess/xsv_fpga/verilog/dbg_interface/timescale.v
    N or1k/xess/xsv_fpga/verilog/mem_if/flash_top.v
    N or1k/xess/xsv_fpga/verilog/mem_if/sram_top.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_alu.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_amultp2_32x32.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_cfgr.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_cpu.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_ctrl.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_dc_fsm.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_dc_ram.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_dc_tag.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_dc_top.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_defines.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_dmmu_tlb.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_dmmu_top.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_dpram_32x32.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_du.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_except.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_freeze.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_genpc.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_gmultp2_32x32.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_ic_fsm.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_ic_ram.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_ic_tag.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_ic_top.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_if.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_immu_tlb.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_immu_top.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_lsu.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_mem2reg.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_mult_mac.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_operandmuxes.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_pic.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_pm.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_reg2mem.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_rf.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_spram_1024x32.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_spram_1024x8.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_spram_2048x32.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_spram_2048x8.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_spram_256x21.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_top.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_spram_512x20.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_spram_64x14.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_spram_64x22.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_spram_64x24.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_sprs.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_tpram_32x32.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_tt.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_wb_biu.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_wbmux.v
    N or1k/xess/xsv_fpga/verilog/or1200/or1200_xcv_ram32x8d.v
    N or1k/xess/xsv_fpga/verilog/or1200/changed.txt
    N or1k/xess/xsv_fpga/verilog/ssvga/crtc_iob.v
    N or1k/xess/xsv_fpga/verilog/ssvga/pci_user_constants.v
    N or1k/xess/xsv_fpga/verilog/ssvga/ssvga_crtc.v
    N or1k/xess/xsv_fpga/verilog/ssvga/ssvga_defines.v
    N or1k/xess/xsv_fpga/verilog/ssvga/ssvga_fifo.v
    N or1k/xess/xsv_fpga/verilog/ssvga/ssvga_top.v
    N or1k/xess/xsv_fpga/verilog/ssvga/ssvga_wbm_if.v
    N or1k/xess/xsv_fpga/verilog/ssvga/ssvga_wbs_if.v
    N or1k/xess/xsv_fpga/verilog/ssvga/timescale.v
    N or1k/xess/xsv_fpga/verilog/ssvga/top.v
    N or1k/xess/xsv_fpga/verilog/uart16550/timescale.v
    N or1k/xess/xsv_fpga/verilog/uart16550/uart_debug_if.v
    N or1k/xess/xsv_fpga/verilog/uart16550/uart_defines.v
    N or1k/xess/xsv_fpga/verilog/uart16550/uart_fifo.v
    N or1k/xess/xsv_fpga/verilog/uart16550/uart_receiver.v
    N or1k/xess/xsv_fpga/verilog/uart16550/uart_regs.v
    N or1k/xess/xsv_fpga/verilog/uart16550/uart_top.v
    N or1k/xess/xsv_fpga/verilog/uart16550/uart_transmitter.v
    N or1k/xess/xsv_fpga/verilog/uart16550/uart_wb.v
    N or1k/xess/xsv_fpga/verilog/ps2/ps2_defines.v
    N or1k/xess/xsv_fpga/verilog/ps2/ps2_io_ctrl.v
    N or1k/xess/xsv_fpga/verilog/ps2/ps2_keyboard.v
    N or1k/xess/xsv_fpga/verilog/ps2/ps2_top.v
    N or1k/xess/xsv_fpga/verilog/ps2/ps2_translation_table.v
    N or1k/xess/xsv_fpga/verilog/ps2/ps2_wb_if.v
    N or1k/xess/xsv_fpga/verilog/ps2/timescale.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_clockgen.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_crc.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_defines.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_fifo.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_maccontrol.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_macstatus.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_miim.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_outputcontrol.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_random.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_receivecontrol.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_register.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_registers.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_rxaddrcheck.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_rxcounters.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_rxethmac.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_rxstatem.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_shiftreg.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_sync_clk1_clk2.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_top.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_transmitcontrol.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_txcounters.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_txethmac.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_txstatem.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_wishbone.v
    N or1k/xess/xsv_fpga/verilog/ethernet/eth_wishbonedma.v
    N or1k/xess/xsv_fpga/verilog/ethernet/generic_spram.v
    N or1k/xess/xsv_fpga/verilog/ethernet/generic_tpram.v
    N or1k/xess/xsv_fpga/verilog/ethernet/timescale.v
    
    No conflicts created by this import
--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml
Prev by Date: [cvs-checkins] ethernet/rtl/verilog eth_rxaddrcheck.v
Next by Date: [cvs-checkins] Import
Prev by thread: [cvs-checkins] Import
Next by thread: [cvs-checkins] Import
Index(es):
- Date
- Thread