[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[oc] Synchron Moore State Machine



Dear VHDL folks,

Using a CPLD, I have made a FIFO buffert control for an external 512kB 
SRAM.  The CPLD controls the read/write cycles. The cycles are 
controlled by a Synchron Moore State Machine.

The State Machine uses One-Hot encoding. 
"When others", is therefore not used.

Problem: The system locks with both read and write active, which is a 
state that I have not defined.

Question: How do I solve this problem, and why do this problem occur? 

Best regards,
Magnus


--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml