[oc] newbie to wishone

[aspoous@yahoo.com]

Hi all,
I am trying to write a converter between an AMBA master and a 
WISHBONE slave.  If it allready exists, please let me know.
I have a problem with the wishbone specification.

1) the master drives everything on the rising edge, but what about the 
slave?  If everything (data, address and control) must be driven in oe 
clock cycle, is the slave then asynchronous, or does it read and drive on 
the falling edge of the clock?

2) If the slave does not respond immediately on the STB signal, then 
wait states are inserted, and everything is delayed, but is it necessary 
that the address remains stable until the ACK signal, or is one clock 
enough?

I hope someone can give me the answer,
thanks and regards,
Aspoous
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