Re: [oc] PUSH/POP Instructions on RISC?

[Johan Klockars <rand@cd.chalmers.se>]

> > > Why are the push/pop instructions never found on risc processors? If a
> > > processor has two write backs to the register file it doesn't need that
> > OR1k doesn't have two write ports...
> Well it's easy to add especially since the regfile is often a dual

It is not at all easy.

> ported ram.

That doesn't help.
You are forgetting that two reads are necessary every cycle besides
the single (or double if you have it your way) write.

Even handling two reads and one write simultaneously requires two
copies of a dual ported RAM. You then use one port on each for the
two separate reads, and write the same thing into both at once.
You can't get two write ports and two read ports simultaneously using
dual port RAM alone. Some extra multiplexing will be needed, at best,
and that costs significant time.

> > > much more hardware to do post/pre-increment/decrement memory reference
> > > instructions. Is there a special reason for not having these

See above.

> > > instructions? It's simpler than a scaled memory reference reg+c*reg.

That it certainly is, and I've never heard of a RISC processor that
has the latter.

As has been mentioned, ARM has something like what you want, and the
PowerPC has something even better with its '...and update' address mode.

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