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Hi! I like to visit the project site at the opencores home page.
However what I miss is a flag or logo to differ from a VHDL project and a
Verilog project. I do believe that this is also an issue for other opencore users.
Some are not familiar with VHDL or Verilog. Others have only a licence for VHDL
or Verilog. It would be great if someone could
add some marking on the projects to identify them as VHDL or Verilog projects. Have a nice day. Robert |