Re: [oc] WISHBONE DMA/Bridge

["Rocky" <trekker@263.net>]

i am just writing,but it's simple,
it is my graduate design, based on intel_8237A_dmac,and simplified.
----- Original Message ----- 
From: Rudolf Usselmann <rudi@asics.ws>
To: <cores@opencores.org>
Sent: Tuesday, March 20, 2001 8:13 PM
Subject: Re: [oc] WISHBONE DMA/Bridge


> on 3/20/01 14:52, Rocky at trekker@263.net wrote:
> 
> > I think in VHDL would be better,because I only understand VHDL, hehe
> 
> 
> Well, why don't you write something in VHDL, he he
> 
> rudi
> 
> > ----- Original Message -----
> > From: "Rudolf Usselmann" <rudi@asics.ws>
> > To: "OPENCORES" <cores@opencores.org>
> > Sent: Monday, March 19, 2001 9:25 PM
> > Subject: [oc] WISHBONE DMA/Bridge
> > 
> > 
> >> 
> >> I have finished the WISHBONE DMA/Bridge IP core and
> >> checked in the Verilog Source code.
> >> 
> >> Please see the "WISHBONE DMA" page for more info.
> >> 
> >> http://www.opencores.org/cores/wb_dma
> >> 
> >> Cheers !
> >> -- 
> >> rudi
>