Re: [oc] Hi

[Jamil Khatib <jamilkhatib75@yahoo.com>]

You are more than welcomed 

You can join any project you like, currently there is
no one working on the USB project so may be you help
us with that.
We do not have any limitations or restrictions on any
thing you can choose your design flow and the language

Please feel free to ask us


Regards
Jamil Khatib
--- Ganesh Chandrasekaran <ganesanc@yahoo.com> wrote:
> 
> 
> Hi,
>   My name is ganesh and I am in ASIC design for the
> past 4 years and I saw your website. I like it and I
> am interested in working with you guys in developing
> few cores. I presently dont have any core in mind
> but
> would like to work on something for which you need
> developers. I have done lot of work on USB Host and
> Device and have done few things on PCI, FIFO etc. I
> would prefer developing in Verilog. Could you please
> give me more details about your organisation and the
> type of work and commitment that you are expecting
> me.
> 
> Thanks
> ganesh
> 
> 
> 
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