[pci] #`FF_DELAY statements in pci_out_reg.v

[Black@intercel.com.cn]

HI,i am reading "pci_out_reg.v"
Inside this file,i find some codes like 

 always@(posedge reset_in or posedge clk_in)
begin
    if ( reset_in )
        dat_out <= #`FF_DELAY 1'b0 ;
    else if ( dat_en_in )
        dat_out <= #`FF_DELAY dat_in ;
end

i am always told that dose not use Wait for XX (vhdl) or #XX(verilog)  
statements in your code  'cause these statements will not be 
Synthesized.However,i found several #'FF_DELAY statements in this file.
It really confuse me.Any comments will be appreciated.
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