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[cvs-checkins] pci/rtl/verilog pci_bridge32.v pci_pciw_fifo_c ...

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	tadejm	03/08/08 18:36:54

Modified files:
	rtl/verilog    : pci_bridge32.v pci_pciw_fifo_control.v 
	                 pci_pciw_pcir_fifos.v pci_target32_interface.v 
	                 pci_target32_sm.v pci_target_unit.v 

Log message:
	Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.

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