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[cvs-checkins] vga_lcd/rtl/verilog vga_defines.v vga_enh_top. ...

CVSROOT:	/home/oc/cvs
Module name:	vga_lcd
Changes by:	rherveille	03/08/01 13:47:23

Modified files:
	rtl/verilog    : vga_defines.v vga_enh_top.v vga_fifo_dc.v 
	                 vga_fifo.v vga_pgen.v vga_wb_master.v 

Log message:
	1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme.
	2) Changed top level and pixel generator to reflect changes in the fifo.
	3) Changed a bug in vga_fifo.
	4) Changed pixel generator and wishbone master to reflect changes.

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