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[oc] Reconfigurable Computing Array (RCA)

I just posted a new project I've been working on lately:

RCA is similar to an FPGA; it's comprised of an array of tiles that 
can be dynamically and partially reconfigured to perform various 
logic functions.

The biggest difference compared to an FPGA is RCA does not have a 
routing matrix.  Instead, each tile is hard-wired to its neareast 
neighbor (North, South, West, East).  The advantages are increased 
logic design and fast deterministic timing.  Signal routing is 
handled by configuring the logic in each tile.

Tiles are fine-grained.  Each has a 4-bit input and a 4-bit output (N, 
S, W, E).  In the current architecture I opted for a 3:1 LUT driving 
each tile output.  The LUT inputs are configurable, each having 3 8:1 
Muxes.  I've drawn up about 6 or 7 tile architectures.  This one 
feels like a good trade-off between area, speed, configuration time, 
and functionality.  Comments and suggestions are welcome.

At this point I'm unsure how well a design can be compiled to such an 
architecture.  On graph paper, I've sketched out a few circuits, such 
as adders, counters, and multipliers.  Doing so, I've noticed a few 
cool techniques including using a tile to compute multiple functions 
in overlaping or in opposite directions (west -> east, west <- east), 
routing data in overlapping or opposite directions, and using tile 
output registers to align the micropipelined data.  In all, it does 
appear to have potential.

The largest array I've posted contains only 256 logic tiles (16x16).  
Anything larger and simulation suffers.  Of course practical 
implementations would have far more tiles, but this is a good size to 
begin experimenting.

If I get time, I'd like to build a custom C model generator that would 
generate a C program to simulate a particular array configuration.  
Confluence generated C is fine for small arrays, but painfully slow 
for huge array sizes.


Tom Hawkins
Launchbird Design Systems, Inc.

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