Re: [video] About DCT cores

[hch93@beethoven.ee.ncku.edu.tw]

----- Original Message ----- 
From: Richard Herveille <richard@a... > 
To: video@o...  
Date: Wed, 8 Jan 2003 09:12:35 +0100 
Subject: Re: [video] About DCT cores 

> 
> 
> 
> 
> You are right, there is limited information available for those 
> cores. 
> First of all, you can try to understand the testbench, it includes 
> a number of 
> real life datasamples. 
> 
> The data is fed the the core as follows: 
> cycle1: dstrb asserted (1 cycle only) 
> cycle2-64: data samples (0-62) 
> cycle65: data sample(63) dstrb asserted (next sample block) 
> 
> A datasample block is an 8x8 matrix in the following format 
> (0,0)(0,1)...(0,6)(0,7) 
> (1,0)(1,1)...(1,6)(1,7) 
> . 
> . 
> (6,0)(6,1)...(6,6)(6,7) 
> (7,0)(7,1)...(7,6)(7,7) 
> 
> The samples are fed sequentually from top to bottom to the core. 
> Thus data-in: 
> 
> (0,0)(0,1)..(0,6)(0,7)(1,0)..(1,7)(2,0)..(2,7)(3,0)..(6,7)(7,0)...(7,7) 
> 
> dstrb is asserted the cycle before (0,0). 
> The core is fully pipelined, a new sample can be calculated every 
> clock cycle. 
> Immediately after the first block is calculated, a second block can 
> be 
> calculated; dstb is asserted the cycle before (0,0), so while the 
> datasample 
> (7,7) from the previous block is send to the core. 
> 
> (x, x)(0,0)...(7,7)(0,0) 
> dstrb         dstrb 
> 
> Richard 
> 

I run the simulation of DCT, and it showed some errors.

463 Data compare error, received ffd, expected ffe.           1
468 Data compare error, received fd2, expected fd3.           2
473 Data compare error, received fe9, expected fea.           3
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