Re: [usb] frequency of operation

[Rudolf Usselmann <rudi@asics.ws>]

On Wednesday 13 March 2002 01:59 pm, you wrote:
> Hi All,
>
> In a usb2.0 according to standards, the max data rate can be
> 480Mbps, That means for a serial bus the frequency at which the
> circuit should work is 480MHz. This is not physible.....

Why not ?  It's not possible to implement the physical interface
section in todays FPGAs but an easy task for an ASIC. An
alternative is to use an external PHY chip. This is what my
USB 2.0 Function core does. I hope I can add a USB 1.1
compliant PHY soft core in the future.

By the way that is "feasible" ...

> How can I design the circuit for lesser frequency.

What you probably want is USB 1.1, which defines data rates
at 1.5 and 12 Mbits per second.

> Thanx in advance.
>
> Prashant.


rudi


--
To unsubscribe from usb mailing list please visit http://www.opencores.org/mailinglists.shtml