Re: [usb] question about the DLL in the UTMI

[Rudolf Usselmann <rudi@asics.ws>]

On Wednesday 19 September 2001 17:11, you wrote:
> Jiang daosan wrote:
> >  Hi, Luis:
> >
> >      Thank you so much for your answer.  However, I think there maybe
> > something
> >
> > to talk about more, As you written:
> > >To design a HS PLL you need an external clock of 480x4 MHz (at least,
> > > I think) to obtain the data signal synchronized with the internally
> > > extracted 480 MHz clock.
> >
> > I was wonder that there is some mistake? As the external clock of 480x4
> > MHz is so high, it may be impossibe in practice. I saw the needed
> > external clock in Phlips ISP1501 is 12MHz. In my opinion, the internal
> > local 480MHz clock is produced by the Clock Multiplier with the
> > external 12MHz Clock in the UTM, And then it was made some Phase delay
> > by the HS DLL to synchronized to the clock of the incoming data. That
> > delayed Clock is the exacted clock. Am I right ?
>
> Yes, sorry, I was thinking on my design...
>
> The delayed clock you are referring is the extracted clock (480 MHz
> one). But, how to
> design in HDL a Digital PLL for HS? I don't know another way of
> syncronizing both clocks (internal and the incoming data one) than
> sampling the incoming data with a quicker clock. Any other idea?
>
>
> ========================================================
> Luis Jose Perez Lafuente      	luis.perez@ds2.es

High Speed USB uses a bit clock of 480 Mhz, Full Speed of 12 Mhz.

A HS PHY uses a analog PLL to recover the 480 Mhz clock. You do not
need a 4x480Mhz clock (unless you do want to design a Digital LL, in which
case you would need at least 4x oversampling).

rudi
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