Re: [pci] CardBus interface

["Chandrashekar" <chandrashekar@rassit.com>]

Hi,

It is correct that all the BAR's are common for the given configuration
space. so it is same as PCI.

The CCLKRUN# which is output from the card is required for the PC Card to
control the CardBus clock signal CCLK, i.e you can indicate the host to
start the clock by asserting this signal and also it indicates the status of
the CCLK to the host.

The CSTSCHG# is an optional signal in CardBus PC Card

regards
Chandrashekar

----- Original Message -----
From: <random_user@163.com>
To: <pci@opencores.org>
Sent: Friday, June 21, 2002 7:30 AM
Subject: RE: [pci] CardBus interface


> I have compared the CardBus spec. with the PCI spec 2.2 and I found
> no difference in using the BARs in the conf.
> I think they are the same in using it.
> I am confused of the CSTSCHG# pin and the CCLKRUN# pin.
> HOW to handle them?
> I don't think the CSTSCHG# pin is of much use.And, it is optional.So,
> can I design a CardBus bridge core without it?
> As for the CCLKRUN# pin,I don't know how to deal with it.
> What's your opinion?
> Any help wiil be appreciated!
>
> regards,
> wangc
>
>
>
> ----- Original Message -----
> From: "Charles Krinke" <ckrinke@p... >
> To: <pci@o... >
> Date: Thu, 20 Jun 2002 08:32:28 -0700
> Subject: RE: [pci] CardBus interface
>
> >
> >
> > I believe the term multifunction in the context of this mailing
> > list and the
> > PCI bridge refers solely to those PCI devices that have more then
> > one
> > function in a single device. This is the term as used by the PCI
> > specification itself. Many Intel chips such as the 82371
> > Northbridge that is
> > on many motherboards and the 80312 Companion chip that I use with
> > the 80200
> > processor are multifunction devices. This means they have more then
> > one
> > Vendor/DeviceID, more then one set of configuration registers and
> > more then
> > one set of functions.
> > In each PCI device, there are several Base Address Registers. It is
> > entirely
> > common for one BAR to address MEM and a second BAR to address IO
> > space in
> > the same PCI device.
> > As for PC CARDS, dont know much about that, know a bit about PCI.
> > Charles
> >
> > -----Original Message-----
> > From: owner-pci@o...
> > [/cgi-bin/post.cgi?cmd=new&to=owner-pci%20at%20opencores%
> 20dot%20org&msg=/ml-archive/pci/msg00044.shtml
> > Behalf
> > Of random_user@1...
> > Sent: Thursday, June 20, 2002 4:17 AM
> > To: pci@o...
> > Subject: Re: [pci] CardBus interface
> >
> >
> > Hi,
> > It looks like that there is no concept of multifunction in the
> > CardBus
> > specification
> > In my opinion,this concept
> > is used in the 16-bit PC CARD specification,in which a CARD can be
> > used
> > only as MEM Card or I/O Card.When a card is used for both MEM and
> > I/O
> > operation ,it is called multifunction Card.
> > But in the CardBus specification and later,the term--multifunction
> > appeared no more.
> > Am I right?If not,can you tell me what's the right ?
> > Thank you for any information.
> > And,I want to know when the PCI bridge core is modified to be used
> > as
> > CardBus bridge core, what,in details,should be modified ?
> > Thanks.
> > regards,
> > wangc
> >
> >
> >
> >
> > ----- Original Message -----
> > From: "Chandrashekar" <chandrashekar@r... >
> > To: <pci@o... >
> > Date: Thu, 20 Jun 2002 10:40:15 +0530
> > Subject: Re: [pci] CardBus interface
> >
> > >
> > >
> > > Hi,
> > >
> > > I refered the PC Card CardBus specification document and it
> > says
> > > the BAR's
> > > usage in case of CardBus is similar to PCI BARs. But one BAR
> > is
> > > sufficient
> > > for one function implemented in the card. For multifunction
> > cardbus
> > > cards,
> > > you have to use as much BAR(max 6) as the no. of
> > multifunctions
> > > implemented
> > > in the card
> > >
> > > regards,
> > > Chandrashekar
> > >
> > > ----- Original Message -----
> > > From: <random_user@1... >
> > > To: <pci@o... >
> > > Sent: Thursday, June 20, 2002 8:09 AM
> > > Subject: Re: [pci] CardBus interface
> > >
> > >
> > > > hi,
> > > > I am working on CardBus interface now.
> > > > I think the base address registers in the conf can be
> > used for
> > > CardBus in
> > > > the same way.Do you think so?
> > > >
> > > > regards,
> > > > wangc
> > > >
> > > > ----- Original Message -----
> > > > From: "Chandrashekar" <chandrashekar@r... >
> > > > To: <pci@o... >
> > > > Date: Wed, 19 Jun 2002 09:46:53 +0530
> > > > Subject: [pci] CardBus interface
> > > >
> > > > > Hi,
> > > > >
> > > > > I need to design CardBus interface. I have PCI open
> > core
> > > downloaded
> > > > > and I have modified it to target only operation. Now
> > I
> > > want to
> > > > > convert the PCI target only design to CardBus
> > design. I
> > > am not very
> > > > > clear about using the Base address register in the
> > > configuration
> > > > > space for the cardbus interface. Does any one
> > working on
> > > CardBus
> > > > > interface? or any information on cardbus interface
> > > design?
> > > > >
> > > > > thanks
> > > > > chandrashekar
> > > > >
> > > >
> > > >
> > >
> >
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