RE: [pci] constrain file

[stevens@dtims.com]

Hey,
I think that I am having the same problem.  I am running the bridge off 
of a Xilinx Spartan II chip.  The project synthesizes and implements fine, 
but DEVSEL will never assert when the PCI bus tries to find the bridge.  
I think the problem may have to do with timing issues and Xilinx's 
Foundation Manager 4.1i's optimization of design.  Does anyone know 
how I can assign a preserve hierarchy using Foundation 4.1's Project 
Manager?  If not for that specific program, how can I do it in general?  I 
am not familiar with this concept.
Thanks for any help,
Steven

----- Original Message ----- 
From: "Tadej" <tadej@o... > 
To: <pci@o... > 
Date: Wed, 12 Jun 2002 15:42:31 +0200 
Subject: RE: [pci] constrain file 

> 
> 
> Hi! 
> 
> I assume you are using the Opencores PCI bridge. 
> On the PCI side, which have high timing constraints, we put 
> some logic into separate files with word "crit" in the name 
> of the files. To these files (or modules) and just to these 
> ones you should assign a preserve hierarchy. 
> That is how they are not optimised with the rest of the logic. 
> With this you should meet timings. 
> 
> Please respond if you will succeed or fail with timings. 
> 
> 
> Best regards, 
> 	Tadej 
> 
> 
> -----Original Message----- 
> From: owner-pci@o...  
> [/cgi-bin/post.cgi?cmd=new&to=owner-pci%20at%20opencores%
20dot%20org&msg=/ml-archive/pci/msg00014.shtml 
> Behalf 
> Of Pinhas.Krengel@f...  
> Sent: Wednesday, June 12, 2002 3:13 PM 
> To: pci@o...  
> Subject: Re: [pci] constrain file 
> 
> 
> Hi 
> Sometimes it is just enough to tell (manual placement) the place 
> and 
> route software just a few critical modules. 
> As you can see in the documentation as well as by the file name, 
> the 
> core's critical modules. Synthesize each of them separatly and 
> manually 
> place them. 
> Then give it a try with a few seeds (assuming you use XILINX 
> tools). 
> 
> ----- Original Message ----- 
> From: "Gvozden Marinkovic" <gvozden@t... > 
> To: <pci@o... > 
> Date: Fri, 7 Jun 2002 17:11:35 +0200 
> Subject: [pci] constrain file 
> 
> > 
> > 
> > Can you send constraint file for synthesis tool (in txt 
> format)? 
> > I cannot meet timing constraints. 
> > 
> > Sincerely, 
> > 
> > Gvozden 
> > 
> 
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