Re: [pci] PCI-Wishbone initialization

["Dave Warren" <dave@luscher.co.uk>]

Charles,

I use the previous generation of the Intel IO controller the 80303 on a
board as an embedded processor. On the PCI bus you can't allow the control
signals to just float. The off condition is high, 3.3 volts, a weak pull up
resistor is needed, say 8K2. Signals to terminate are SERR, PERR, LOCK,
STOP, DEVSEL, TRDY, IRDY, FRAME, PAR64, ACK64. Also disable 66Mhz operation
by grounding pin B49.

Dave Warren

----- Original Message -----
From: "cfk" <cfk@pacbell.net>
To: <pci@opencores.org>
Sent: Friday, June 07, 2002 8:00 PM
Subject: [pci] PCI-Wishbone initialization


> I have gotten to the stage where I can synthesize and implement in a
VirtexE
> 2000 the PCI-Wishbone  bridge with GUEST defined. In my particular design,
> there is no motherboard and CPU on the PCI bus. I have two PCI devices,
one
> impmented in the VirtexE consisting of the PCI-Wishbone bridge, an arbiter
> (just two REQ/GNT pairs), and a system controller to provide RST and
PCICLK.
> The second device connected to the PCI bus is a PCI730 card from
> http://www.cyclone.com . This card consists of an Intel 80200 XScale CPU
and
> an Intel 80312 Companion chip amongst other things. The PCI730 runs
vxWorks,
> and I control the code running on the PCI730. I also have a PC system unit
> with the CPU unplugged that provides a PCICLK, RST that is my A/B
> comparision.
>
> The current situation is that I have gotten to where I can assert/deassert
> RST and emit a clean PCICLK. I did have some over/undershoot issues that I
> solved on the clock yesterday. Basically, when I plug the PCI730 into the
PC
> system unit, it comes out of reset, initializes its CPU and starts talking
> RS-232 no problem. But when I plug the same PCI730 into my board with a
> VirtexE which has my system controller logic and the PCI-Wishbone bridge,
> the PCI730 gets hung up around the initialization of its MMU subsystem and
> never completes.
>
> At this point, I can see that the PCI bus is in a static condition on both
> systems. On the PC system unit, I can see that AD[31:0] is all bits lo,
> CBE[3:0] is 4'b1011, RST, STOP, FRAME, IRDY, TRDY, DEVSEL & GNT are hi
> (de-asserted) and REQ, PAR, SERR & PERR are lo.  On my custom board with
the
> PCI-Wishbone bridge inside it, I can see that all of the previous lines
are
> hi. It appears that the PC system unit is asserting some of these lines
even
> without a CPU.
>
> Can someone provide some insight on where to begin looking next? I think
my
> choices are:
>
> 1) The 80312 is in an error condition because one or more of the PCI lines
> mentioned above is in the wrong state?
> 2) The 80312 is in an error condition because some line I am not looking
at
> is in the wrong state (LOCK, REQ64/GNT64/PAR64)?
> 3) Perhaps I have not signalled the 3.3PCI lines to tell the PCI730 that
he
> is on a 3.3PCI bus instead of a 5V bus (it is a universal card, I think I
> got it right, but maybe not)?
> 3) Maybe my system controller needs to assert AD[31:0], CBE[3:0], REQ,
PAR,
> PERR, SERR when the bus is idle?
> 5) The **unexpected**.
>
> Charles
>
>
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