Re: [openrisc] CID bits in OR1000 and OR1200

[Marko Mlinar <markom@opencores.org>]

On Wednesday 16 October 2002 20:50, mbtirado@mundivia.es wrote:
> Hello.
> I have been studying OR1000 Architecture and OR1200 implementation.
> There are some features that don't appear clearly to me. These are
> related to CID (Context ID) bits.
> Let's consider an implementation based on OR1000 architecture. Can
> you implement CID bits (I mean, its functionallity: CID automatic
> incrementing) without implementing any set of shadow registers? I think
> this option should be possible, but in the OR1000 Architecture Manual it
> seems to be obligatory to implement both (CID bits and shadow
> registers) or none (see page 28: SR[CE] - CID Enable).
> However, in the OR1200 IP Core Specification it is clear that shadow
> registers are not used, as you can see in page 53 (CPUCFGR
> Description), but in figure 10 (Address Translation Mechanism) you can
> see that CID bits are used for address translation in MMU. So if this
> were correct, the answer to my first question would be affirmative.
> However, as far as I have read source code of OR1200, I am almost sure
> that CID bits aren't used, so I am very confused about the whole thing.
> Could figure 10 in page 38 of OR1200 IP Core Specification be wrong? I
> would be very grateful if anybody can help.
> Thank you very much.

Even when CIDs are not used, concept is the same, with only exception -- 
SR[CID] is aways constant 0. Thus the or1200 CID core functionality can be 
made very simple, and images can be reused ;)

Marko



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