[openrisc] OpenRISC target for GUSS

[Johan Rydberg <jrydberg@rtmk.org>]

I'm working on a simulator system call GUSS (stands for
GUSS the Universal System Simulator).  To try out the design
I made a simple OpenRISC target for it.  The code is not yet
commited to CVS, but hopefully will be within the next days or 
within a week or so.  

The target is not finished yet, but it's able to boot uClinux 
into the cpu_idle loop.  UART output:

OpenRisc 1000 support (C) www.opencores.org


uClinux/OR32
Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne
KERNEL -> TEXT=0x4002000-0x4095d08 DATA=0x002000-0x00abfc BSS=0x00ac00-0x02b6ad
KERNEL -> ROMFS=0x02b6ad-0x02b6b0 MEM=0x02b6b0-0x7ff000 STACK=0x7ff000-0x800000
Command line: 'CONSOLE=/dev/ttyS0'
Done setup_arch
Calibrating delay loop.. ok - 4.32 BogoMIPS
Memory available: 7896k/8180k RAM, 0k/0k ROM (292k kernel data, 599k code)
Swansea University Computer Society NET3.035 for Linux 2.0
NET3: Unix domain sockets 0.13 for Linux NET3.035.
Swansea University Computer Society TCP/IP for NET3.034
IP Protocols: ICMP, UDP, TCP
uClinux version 2.0.38.1pre3 (jrydberg@cockmaster) (gcc version 3.1 20020121 (experimental)) #8 Wed Jun 19 04:25:08 CEST 2002


It executes roughly 40 simulated MIPS (on my P3 @ 800 MHz), 
but a lot of optimizations are left to do.  

I know you use or1ksim, but I just wanted to let you know of 
my work.  Hopefully, sometime in the future, GUSS will have 
more features than or1ksim, and be (magnitudes) faster.

I'll try to incorporate all simulated hardware that exist 
in or1ksim (such as dma, ethernet, ...).

You can find more information about GUSS at:

  http://savannah.gnu.org/projects/guss/

regards
johan

ps. i'm not subscribed to the list, so if you wanna 
reply to this mail, CC me.  ds.
--
To unsubscribe from openrisc mailing list please visit http://www.opencores.org/mailinglists.shtml