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[openrisc] Verilog version of OpenRISC 1001
I've translated the OpenRISC 1001 VHDL code to Verilog so
I can play with it more easily. It does seem to run most
of the testbench code provided in the cpu_TB module, though
the memory store gets skipped (does this happen with the
VHDL as well?). Runs fine under the free Icarus Verilog
simulator (http://icarus.com/eda/verilog), by the way
(using the current development snapshot).
Comments welcome. I hope to track the VHDL changes as they
become available.
A preliminary synthesis with Synplify shows that it occupies
about 34% of an Altera 10K50E-2 (~1000 logic cells). Most
of it seems to run at around 50 MHz on this part---unfortunately
Synplify chose a ripple structure for a magnitude comparator
("a>b"), so I'll have to replace that with something faster
to get a hard speed number.
I'll just attach the code (it's only 10kByte compressed);
sorry to spam people with this, but I don't really have a
sensible place to put it.
Cheers,
Peter Monta pmonta@terayon.com
Terayon Communication Systems
or1k-verilog.tar.gz