[openrisc] Re: delay slot problem

["Damjan Lampret" <lampret@opencores.org>]

> Hi Damjan,
> Since unconditional branch is always taken, the insn in the delay slot
> could be always executed. But the delay slot in the conditional branch
> would enlarge the program size and the insn in the delay slot is not
> always executed. If I can't insert appropriate insn in the conditional
> branch delay slot, then h.nop must be inserted. That would cost
> a lot of insn in the conditional delay slot without increasing
performance.
> And the delay slot of unconditional(always taken) branch/jump could
> always(often) insert useful insn. That's what I want :)
>

Ahha ! Interesting. I see delay slot from performance point of view (not
like you from the program size POV). So in my case I don't care about some
empty delay slots since delay slots always keep my pipeline as full as
possible. See file testbench/dhry.or1k in or1ksim and check what is the
number of filled and empty delay slots. This is dhrystone benchmark compiled
for OR32 (the old or32).

> Right! I have solve the delay slot problems. I use one flag. I hope it's
not
> a stupid method.
>
> ..in the sequence
> h.load32u r3, 0x5(r1)
> h.add32s  r2,r3
>
> the insn(h.add32s) immediately following h.load32u is using the content
> of the r3. So, if compiler doesn't insert h.nop or one useful insn, then
> hardware has to insert one bubble.
> h.mfsr has similar situation..
> How do you think?

Ahha. I don't call this delay slot. I call it RAW hazard (read-after-write
hazard). Basically you need to stall the pipeline at decode stage and insert
a nop in the pipeline (a bubble). BTW you can't predict how long load insn
will take since you don't know what is happening outside of the processor
(perhaps the processor doesn't own the bus or there is a data cache miss).
So load insn can take variable number of cycles to complete. How one checks
for RAW hazards?

Perhaps like this (asynchronously we disable IF, ID stages and insert a
bubble but this is not show here - only detection according to insns in the
IF and issue stages. Also see that RAW occurs only when the previous insn in
the pipeline writes to register file.):

--
-- Detect RAW hazards
--
p_raw_hazard:
process(id_opcode, id_reg_a, id_reg_b, is_rfenw, is_reg_d)
begin
  -- check for RAW and if it exists insert a bubble in IS stage
  if (id_opcode(5) = '1' and is_rfenw = '1' and id_reg_a = is_reg_d) or
   (id_opcode(4) = '1' and is_rfenw = '1' and id_reg_b = is_reg_d) then
   raw_hazard <= '1';
  else
   raw_hazard <= '0';
  end if;
end process;

regards, Damjan