Re: Fwd: [ethmac] Minimum clock frequence?

[Peter Magnusson <bluefish@swipnet.se>]

Hi Igor and Marc!

> nice e-mail address (bluefish) ;-)))

Thanks :-)

> I have implemented the design with 33MHz and know that it is running with 
> 75 MHz (just for your information).

It does 100 MBit in 33 MHz? That's much better than e.g. Xilinx EMAC and
EMAC Lite which has a minimum of 50 MHz (or 5 MHz for 10 MBit). 

I've designed a small MAC (very simple compared to your MAC) and got a
estimated minimum clock frequency of 31 MHz (due to two asynchrounous open
loop transition between rx/txclk and system clock domain). However, in
simulations it performs OK at lower frequences. So I suspect that
simulations may yield better results than which the device actually is
gauranteed to work with (because simulation may not find all race
conditions)

Still, simulations will do fine in lack of other means. I'll have a look
at it later on, and if I get any results I'll get back to you on the
subject.

> But I never tried it out how slow I could get, because normally the 
> customer can't have enough performance.
> Do you have a batterie powered, means low power design?

Actually, I'm only comparing the design to a couple of others as a part of
my thesis. But yes, low power design through low frequency is one of the
topics covered. The folks at my institution like low power designs, they
do some small embedded battery powered systems and some research on low
power CMOS, so I guessed my supervisor would enjoy such comparisions.

Regards,
  Peter


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