RE: [ethmac] WishBone bug?

["Igor Mohor" <igorm@opencores.org>]

Hi, Torbjörn and Mathias.

Ok, I see know what's wrong. The memory controller or whatever is connected
on the other side of the Ethernet WISHBONE master interface generates
acknowledge signal m_wb_ack_i. An assumption has been made that acknowledge
signal is delayed at least one clock signal (that's the minimum when ack
signal
is registered).

Best regards,
	Igor

> -----Original Message-----
> From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On
> Behalf Of Torbjoern Aronsson
> Sent: 1. oktober 2002 12:34
> To: ethmac@opencores.org
> Subject: [ethmac] WishBone bug?
>
>
> Hello Igor
>
> We use the latest release of Ethmac and we encountered some
> problems. We don't
> use the eth_cop as the ethmac's top level (I hope that isn't the
> problem.)
> If you look at the attached gif you will se a WishBone transfer
> go wrong. At the
> marker, you initialise a wishbone transfer for address 40005a54,
> we give the
> data and confirms it with an ack_i. The cyc_o and stb_o signals
> stays high for
> another clk_cycle. This indicates a burst transfer or that you
> want to read the
> same address once more, but the cyc_o and stb_o goes low without
> a new ack_i
> signal, This is not right.
> The next transfer is for address 40005a5c. Where is the 40005a58
> transfer?
> Something has gone wrong.
>
> And when you're at it... is it possible to make burst transfers work?
>
> /Torbjörn and Mathias
>


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