Re: [ecc] Reed Solomon decoder

[Duane Clark <dclark@akamail.com>]

Duane Clark wrote:
> 
> I will just say that I exploit the structure of the LUT in the Xilinx 
> Virtex chips, and can make a very compact multiplier that can do a GF 
> multiplication in 2 clocks at over 100MHz. It turns out that the Virtex 
> LUT structure is ideally suited to this operation. The 2 clocks are 
> because I pipeline the circuitry, so there are FFs in the middle and at 
> the end of the multiplier (FFs are basically free anyway). All the 
> actual logic is purely combinatorial, without feedback, and without 
> lookup tables. The actual implementation is left as an exercise for the 
> reader:-)

Oops. Everywhere I said LUT up there, replace it with CLB.

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