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[ecc] Reed Solomon decoder

To: ecc@opencores.org
Subject: [ecc] Reed Solomon decoder
From: inada@singnet.com.sg
Date: Wed, 12 Mar 2003 06:06:31 -0100
Reply-To: ecc@opencores.org
Sender: owner-ecc@opencores.org

Hi,
I'm implementing Reed Solomon (255,223) on FPGA using VHDL. I've 
implemented a RS(15,11) as a prototype and it works fine. however, i 
faced trouble when i try upscale it to (255,223) which used up a huge 
number of gates and slices. I believe this is mainly due to the finite field 
conversion(exponential to binary) table implemented in the code. Is 
there any way shorter/more effective way of implementating the finite 
field conversion? other ideas on the code are welcomed!!! Please help!!
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