Re: [ecc] clock domain synchronization

["Damjan Lampret" <lampret@opencores.org>]

Hi Dali,

the list is alive but I don't know how many developers are alive.

regards,
Damjan

----- Original Message -----
From: <mohamed.kilani_ecc@m4x.org>
To: <ecc@opencores.org>
Sent: Monday, October 29, 2001 1:35 AM
Subject: Re: [ecc] clock domain synchronization


> Hi
>
> I am new in the Viterbi project and I am wondering if the mailing list
> is still alive since I tried several times to post a message but got
> "Host Unknown" replies ...
>
> If anyone gets this message please reply.
>
> thanks
>
> Dali
>
>
> ----- Original Message -----
> From: Yu Yang <yu@o... >
> To: ecc newsgrp <ecc@o... >
> Date: Mon, 08 Oct 2001 10:47:37 +0800
> Subject: [ecc] clock domain synchronization
>
> >
> >
> > Hi,
> >
> > I am having trouble implementing a symbol synchronizer (correlator)
> > for
> > bluetooth.
> > I need to regenerate 1m clock from rxd data, output resampled data
> > to
> > the packet
> > decomposer @ clk1m.
> >
> > It is recommended to use a 2-stage synchronizer,  to avoid cross
> > clock
> > domain timing problem
> > This to say the data should be synchronized with at least 2 f/fs
> > before
> > sampling.
> > I am just wodering if the code below can work as expected.
> >
> > always @ (posedge clk24m) begin
> > if (cnt_24 == phase_pos) // 1M timing regeration from clk24m
> >      m0 <= a&b;
> >      m1<= m0;
> > end
> >
> > always @ (posedge clk1m) begin // resample and output @ clk1m
> >     z <= m1;
> > end
> >
> --
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