[cvs-checkins] Import

[OpenCores CVS Agent <cvs@www.opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	camera
Changes by:	oc	03/05/12 12:07:59

Log message:
    Camera IP Core
    
    Status:
    
    Vendor Tag:	TADEJM
    Release Tags:	rel_01
    
    N camera/syn/xilinx/constraints/camera.sdc
    N camera/syn/xilinx/constraints/camera.ucf
    N camera/sim/rtl_sim/run/clean
    N camera/sim/rtl_sim/run/ncsim.args
    N camera/sim/rtl_sim/run/ncsim.key
    N camera/sim/rtl_sim/run/ncvlog.args
    N camera/sim/rtl_sim/run/README.txt
    N camera/sim/rtl_sim/run/run_cam_sim_regr.scr
    N camera/sim/rtl_sim/run/top_groups.do
    N camera/sim/rtl_sim/out/dir_keeper
    N camera/sim/rtl_sim/log/ncelab_xilinx.log
    N camera/sim/rtl_sim/log/ncsim.log
    N camera/sim/rtl_sim/log/ncvlog.log
    N camera/sim/rtl_sim/bin/artisan_file_list.lst
    N camera/sim/rtl_sim/bin/cds.lib
    N camera/sim/rtl_sim/bin/hdl.var
    N camera/sim/rtl_sim/bin/ncelab.args
    N camera/sim/rtl_sim/bin/ncelab_xilinx.args
    N camera/sim/rtl_sim/bin/ncsim.rc
    N camera/sim/rtl_sim/bin/ncsim_waves.rc
    N camera/sim/rtl_sim/bin/rtl_file_list.lst
    N camera/sim/rtl_sim/bin/sim_file_list.lst
    N camera/sim/rtl_sim/bin/xilinx_file_list.lst
    N camera/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper
    N camera/sim/core_sw_simulator/b_cb.dat
    N camera/sim/core_sw_simulator/g_cb.dat
    N camera/sim/core_sw_simulator/g_cr.dat
    N camera/sim/core_sw_simulator/gen_yuv_rgb_files
    N camera/sim/core_sw_simulator/gen_yuv_rgb_files.c
    N camera/sim/core_sw_simulator/r_cr.dat
    N camera/sim/core_sw_simulator/rgb_out.dat
    N camera/sim/core_sw_simulator/rgb_y.dat
    N camera/sim/core_sw_simulator/uyvy_in.dat
    N camera/sim/core_sw_simulator/yuv422_to_rgb
    N camera/sim/core_sw_simulator/yuv422_to_rgb.c
    N camera/rtl/verilog/async_reset_flop.v
    N camera/rtl/verilog/camera_cb_table.v
    N camera/rtl/verilog/camera_cr_table.v
    N camera/rtl/verilog/camera_defines.v
    N camera/rtl/verilog/camera_fifo.v
    N camera/rtl/verilog/camera_fifo_ctrl.v
    N camera/rtl/verilog/camera_io_calc.v
    N camera/rtl/verilog/camera_sync_ctrl.v
    N camera/rtl/verilog/camera_top.v
    N camera/rtl/verilog/camera_tpram.v
    N camera/rtl/verilog/camera_wb_if.v
    N camera/rtl/verilog/camera_y_table.v
    N camera/rtl/verilog/synchronizer_flop.v
    N camera/rtl/verilog/timescale.v
    N camera/bench/verilog/wb_slave_behavioral.v
    N camera/bench/verilog/camera_bench_defines.v
    N camera/bench/verilog/camera_bench_top.v
    N camera/bench/verilog/wb_master_behavioral.v
    N camera/bench/verilog/wb_master_defines.v
    N camera/bench/verilog/wb_master32.v
    
    No conflicts created by this import
--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml