[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[cvs-checkins] oc8051/rtl/verilog oc8051_alu.v oc8051_comp.v ...
CVSROOT: /home/oc/cvs
Module name: oc8051
Changes by: simont 03/04/25 16:15:53
Modified files:
rtl/verilog : oc8051_alu.v oc8051_comp.v oc8051_decoder.v
oc8051_defines.v oc8051_memory_interface.v
oc8051_sfr.v oc8051_top.v
Log message:
change branch instruction execution (reduse needed clock periods).
--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml