[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] can/ ench/verilog/can_testbench.v tl/verilog/c ...

CVSROOT:	/home/oc/cvs
Module name:	can
Changes by:	mohor	03/02/14 19:17:13

Modified files:
	bench/verilog  : can_testbench.v 
	rtl/verilog    : can_bsp.v can_btl.v can_fifo.v can_registers.v 
	                 can_top.v 
	sim/rtl_sim/run: wave.do 

Log message:
	Several registers added. Not finished, yet.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml