[cvs-checkins] i2c/rtl vhdl/i2c_master_bit_ctrl.vhd verilog/i ...

[OpenCores CVS Agent <cvs@www.lampret.com>]

CVSROOT:	/home/oc/cvs
Module name:	i2c
Changes by:	rherveille	03/02/04 23:06:15

Modified files:
	rtl/vhdl       : i2c_master_bit_ctrl.vhd 
	rtl/verilog    : i2c_master_bit_ctrl.v 

Log message:
	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.

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