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[cvs-checkins] can/ ench/verilog/can_testbench.v tl/verilog/c ...
CVSROOT: /home/oc/cvs
Module name: can
Changes by: mohor 03/02/04 13:35:08
Modified files:
bench/verilog : can_testbench.v
rtl/verilog : can_bsp.v can_top.v
sim/rtl_sim/bin: rtl_file_list
sim/rtl_sim/run: wave.do
Added files:
rtl/verilog : can_ibo.v
Log message:
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