[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] ethernet/rtl/verilog eth_top.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] ethernet/rtl/verilog eth_top.v
From: OpenCores CVS Agent <cvs@www.lampret.com>
Date: Tue, 19 Nov 2002 16:34:25 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/11/19 16:34:25

Modified files:
	rtl/verilog    : eth_top.v 

Log message:
	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
	that a frame was received because of the promiscous mode.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml

Prev by Date: [cvs-checkins] ethernet/rtl/verilog eth_wishbone.v
Next by Date: [cvs-checkins] ethernet/rtl/verilog eth_rxaddrcheck.v
Prev by thread: [cvs-checkins] ethernet/rtl/verilog eth_top.v
Next by thread: [cvs-checkins] ethernet/rtl/verilog eth_top.v
Index(es):
- Date
- Thread