[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] dividers/bench/verilog bench_div_top.v timescale.v

CVSROOT:	/home/oc/cvs
Module name:	dividers
Changes by:	rherveille	02/10/31 12:53:56

Modified files:
	bench/verilog  : bench_div_top.v 
Added files:
	bench/verilog  : timescale.v 

Log message:
	Modified testbench. Fixed a bug in the remainder output size of div_su.v

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml