CVSROOT: /home/oc/cvs Module name: pci Changes by: mihad 02/10/14 11:23:32 Modified files: bench/verilog : pci_testbench_defines.v rtl/verilog : pciw_fifo_control.v Log message: Changed empty status generation in pciw_fifo_control.v -- To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml