[cvs-checkins] pci/ ench/verilog/pci_testbench_defines.v ench ...

[OpenCores CVS Agent <cvs@www.lampret.com>]

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	02/10/11 09:09:03

Modified files:
	bench/verilog  : pci_testbench_defines.v system.v 
	                 wb_slave_behavioral.v 
	rtl/verilog    : pci_bridge32.v pci_target_unit.v pci_tpram.v 
	                 pciw_pcir_fifos.v top.v wb_slave_unit.v 
	                 wb_tpram.v wbw_wbr_fifos.v 
	sim/rtl_sim/run: run_pci_sim_regr.scr 

Log message:
	Added additional testcase and changed rst name in BIST to trst

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