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[cvs-checkins] dbg_interface/rtl/verilog dbg_register.v dbg_r ...

CVSROOT:	/home/oc/cvs
Module name:	dbg_interface
Changes by:	mohor	02/10/10 01:43:28

Modified files:
	rtl/verilog    : dbg_register.v dbg_registers.v dbg_top.v 

Log message:
	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.

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