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[cvs-checkins] wb_conmax/ ench/verilog/test_bench_top.v ench/ ...
CVSROOT: /home/oc/cvs
Module name: wb_conmax
Changes by: rudi 02/10/03 04:40:10
Modified files:
bench/verilog : test_bench_top.v wb_mast_model.v
wb_model_defines.v wb_slv_model.v
doc : STATUS.txt conmax.pdf
rtl/verilog : wb_conmax_arb.v wb_conmax_defines.v
wb_conmax_master_if.v wb_conmax_msel.v
wb_conmax_pri_dec.v wb_conmax_pri_enc.v
wb_conmax_rf.v wb_conmax_slave_if.v
wb_conmax_top.v
sim/rtl_sim/bin: Makefile
syn/bin : comp.dc
Log message:
Fixed a minor bug in parameter passing, updated headers and specification.
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